Semiconductor device and method for manufacturing the same

ABSTRACT

An MISFET has a gate electrode formed on a semiconductor substrate via a gate insulating film, and a source region and a drain region formed inside the semiconductor substrate so as to sandwich the gate electrode. And, a first silicide layer is formed on surfaces of the source region and the drain region, and a second silicide layer is formed on a surface of the gate electrode. Each of the first silicide layer and the second silicide layer is made of a first metal and silicon, and further contains a second metal different from the first metal. And, a concentration of the second metal inside the second silicide layer is lower than a concentration of the second metal inside the first silicide layer.

TECHNICAL FIELD

The present invention relates to a semiconductor device and a method formanufacturing the same, and is preferably applicable to, for example, asemiconductor device having a nonvolatile memory and a method formanufacturing the same.

BACKGROUND ART

As a semiconductor device having a memory cell of an electricallywritable/erasable nonvolatile memory, a memory cell including aconductive floating gate electrode surrounded by an oxide film or atrapping insulating film sandwiched by an oxide film below the gateelectrode of the MISFET is widely used. The latter is referred to as aMONOS (Metal Oxide Nitride Oxide Semiconductor) type including a singlegate type cell and a split gate type cell, and is used as a nonvolatilememory of a microcomputer.

In accordance with achievement of lower power consumption and highintegration of the microcomputer, a transistor including a metal gateelectrode and a high dielectric constant film (high-k film) is used in alogic portion. As a method for forming such a transistor, so-called agate-last process is known, the gate-last process forming a source/drainregion by using a dummy gate electrode made of a polycrystalline siliconfilm on a substrate, and then, replacing the dummy gate electrode with ametal gate electrode.

In the gate last process, after a silicide layer is formed on thesource/drain region of various MISFETs, an element is covered with aninterlayer insulating film, and then, an upper surface of the interlayerinsulating film is polished to expose an upper surface of the gateelectrode. For this reason, when a silicide layer is formed on a gateelectrode configuring a memory cell and being made of a semiconductorfilm, it is required to form the silicide layer again after thepolishing process.

Patent Document 1 (Japanese Patent Application Laid-open Publication No.2014-154790) describes a case of mixedly mounting the memory cell andthe MISFET of the logic portion, in which a silicide layer is formed ona source/drain region of the MISFET, subsequently a metal gate electrodeof the MISFET is formed by the gate-last process, and then, a silicidelayer is formed on the gate electrode of the memory cell.

Patent Document 2 (Japanese Patent Application Laid-Open Publication No.2007-335834) describes a configuration in which in order to set anappropriate threshold value voltage in an n-type FET and a p-type FEThaving a full silicide gate, in the n-type FET, a gate electrode made ofnickel silicide having a nickel content higher than a silicon content isformed on the gate insulating film with an aluminum layer beinginterposed therebetween. Moreover, it is described that in the p-typeFET, a gate electrode made of nickel silicide having a nickel contenthigher than a silicon content is formed on the gate insulating film.Furthermore, on the surface of the source/drain region of the n-type FETand the p-type FET, a silicide layer is formed.

RELATED ART DOCUMENTS Patent Documents

Patent Document 1: Japanese Patent Application Laid-Open Publication No.2014-154790

Patent Document 2: Japanese Patent Application Laid-Open Publication No.2007-335834

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

In a semiconductor device having a nonvolatile memory that has beenstudied by the inventor of the present application, the gate electrodeof the MISFET of the logic part is formed by using the gate lastprocess. That is, a first silicide layer is formed on the memory celland the source/drain region of the MISFET of the logic part, and themetal gate electrode of the MISFET of the logic part is formed, andthen, a second silicide layer is formed on the gate electrode of theMISFET of the memory cell. Meanwhile, the first silicide layer and thesecond silicide layer have the same composition as each other.

An object of the present application is to ensure reliability of asemiconductor device. Moreover, another object is to improve aperformance of the semiconductor device.

Other object and novel characteristics will be apparent from thedescription of the present specification and the accompanying drawings.

Means for Solving the Problems

According to one embodiment, the MISFET has a gate electrode formed on asemiconductor substrate via a gate insulating film and a source/drainregion formed inside the semiconductor substrate so as to sandwich thegate electrode. A first silicide layer is formed on a surface of thesource/drain region, and a second silicide layer is formed on a surfaceof the gate electrode. Each of the first silicide layer and the secondsilicide layer is made of a first metal and silicon, and contains asecond metal different from the first metal. Moreover, a concentrationof the second metal in the second silicide layer is lower than aconcentration of the second metal in the first silicide layer.

Effects of the Invention

According to one embodiment, the reliability of the semiconductor devicecan be ensured. Moreover, the performance of the semiconductor devicecan be improved.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a principal part of a semiconductordevice according to one embodiment;

FIG. 2 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device of one embodiment;

FIG. 3 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.2;

FIG. 4 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.3;

FIG. 5 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.4;

FIG. 6 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.5;

FIG. 7 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.6;

FIG. 8 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.7;

FIG. 9 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.8;

FIG. 10 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.9;

FIG. 11 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.10;

FIG. 12 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.11;

FIG. 13 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.12;

FIG. 14 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.13;

FIG. 15 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.14;

FIG. 16 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.15;

FIG. 17 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.16;

FIG. 18 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.17;

FIG. 19 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.18; and

FIG. 20 is a cross-sectional view of a principal part during amanufacturing process of the semiconductor device, continued from FIG.19.

BEST MODE FOR PERFORMING THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail based on the accompanying drawings. Note that components havingthe same function are denoted by the same reference symbols throughoutall the drawings for describing the embodiments, and the repetitivedescription thereof will be omitted. Also, in the following embodiments,explanation of the same or similar parts is not repeated in principleunless particularly required.

In addition, symbols “−” and “+” represent relative concentrations ofimpurities whose conductivity type is n-type or p-type. For example, inthe case of n-type impurities, the impurity concentrations increase inthe order of “n⁻” to “n⁺”.

A semiconductor device (semiconductor integrated circuit device) of thepresent embodiment is a semiconductor device including a nonvolatilememory (a nonvolatile storage element, a flash memory) such as amicrocomputer. The microcomputer includes a CPU (Central ProcessingUnit), a RAM (Random Access Memory), an EEPROM (Electrically ErasableProgrammable Read Only Memory), a flash memory and an I/O (Input/Output)circuit, etc. The CPU requires high-speed operations and low powerconsumption, and therefore, is configured by a MISFET (MISFET: MetalInsulator Semiconductor Field Effect Transistor) being driven at a lowvoltage (for example, 5V or less) and having a low breakdown voltagewith a low threshold value. The EEPROM or the flash memory has aplurality of nonvolatile memory cells disposed into a matrix form, and acontrol circuit for performing writing, erasing and reading operationson the nonvolatile memory cells. Particularly, in the writing anderasing operations, since a high voltage is applied to the nonvolatilememory cells, a MISFET being driven at a high voltage (for example, 10Vor more) and having a high breakdown voltage is included in the controlcircuit.

The nonvolatile memory will be explained while exemplifying a memorycell based on an n-channel type MISFET. However, a p-channel type MISFETmay be exemplified. The CPU and control circuit are configured by ann-channel type MISFET and a p-channel type MISFET. However, here, theexplanation will be made while exemplifying an n-channel type MISFET.

<Configuration of Semiconductor Device>

FIG. 1 is a cross-sectional view of a principal part of thesemiconductor device of the present embodiment. FIG. 1 shows a memorycell region 1A on the left side, a peripheral circuit region 1B at thecenter, and a peripheral circuit region 1C on the right side. A memorycell MC of a nonvolatile memory is formed in the memory cell region 1A,a low breakdown voltage MISFET (Q1) is formed in the peripheral circuitregion 1B, and the high breakdown voltage MISFET (Q2) is formed in theperipheral circuit region 1C. As described above, when the referencesymbol portion is indefinite, parentheses are given to the referencesymbol.

As shown in FIG. 1, the semiconductor device is formed on the mainsurface of the semiconductor substrate SB. The semiconductor substrateSB is a semiconductor wafer made of, for example, a p-type singlecrystal silicon or others having a specific resistance in a range ofabout 1 to 10 Ωcm. In the present embodiment, in order to achieve thehigh speed operation of the p-channel type MISFET, the channel direction(direction connecting the source region and the drain region) of thep-channel type MISFET on the (100) plane of the single crystal siliconsubstrate is set to <110> or <100>. Moreover, the channel direction ofthe n-channel type MISFET (direction connecting the source region andthe drain region) thereon is also set to <110> or <100>.

First, the configuration of the n-channel type memory cell MC formed inthe memory cell region 1A will be described.

In the memory cell region 1A, the semiconductor device has an activeregion and an element isolation region ST formed on the main surface ofthe semiconductor substrate SB. The element isolation region ST is usedfor isolating elements (memory cells) formed in the active region. Inthe element isolation region ST, an element isolation film made of asilicon oxide film or others is formed. The active region is surroundedby the element isolation region ST, and is defined, that is, partitionedby the element isolation region ST. Although not shown, the memory cellregion 1A has a plurality of the active regions, and the plurality ofactive regions are electrically isolated from each other by the elementisolation region ST. In the memory cell region 1A, a p-type well PW1having a p-conductivity type on which the plurality of memory cells MCare disposed is formed.

The memory cell MC is a memory cell of a split gate type. In otherwords, as shown in FIG. 1, the memory cell MC is formed inside thep-type well PW1, and has the control gate electrode CG and the memorygate electrode MG. The memory cell MC has an n-type extension region(n⁻-type semiconductor region, low concentration region, impuritydiffusion region) EX, an n-type diffusion region (n′-type semiconductorregion, a high concentration region, an impurity diffusion region) DF, acontrol gate electrode CG, and a memory gate electrode MG. Each of then-type extension region EX and the n-type diffusion region DF has ann-conductivity type that is an opposite conductivity type to thep-conductivity type.

Moreover, the memory cell MC has a silicide layer (gate silicide layer)S2 formed on the upper surface of the control gate electrode CG and theupper surface of the memory gate electrode MG, and also has a silicidelayer (SD silicide layer) S1 formed on the upper surface of thediffusion region DF.

Furthermore, the memory cell MC has a gate insulating film GIt formedbetween the control gate electrode CG and the semiconductor substrate SB(or the p-type well PW1) and a gate insulating film GIm formed betweenthe memory gate electrode MG and the semiconductor substrate SB (or thep-type well PW1) and between the memory gate electrode MG and thecontrol gate electrode CG.

The control gate electrode CG and the memory gate electrode MG areextended along the main surface of the semiconductor substrate SB anddisposed side by side between their opposed side surfaces to each other,that is, between their sidewalls, via the gate insulating film GIm. Eachextending direction of the control gate electrode CG and the memory gateelectrode MG is a direction perpendicular to the drawing sheet ofFIG. 1. In the plurality (for example, several tens to several hundreds)of memory cells MC arranged in the direction perpendicular to thedrawing sheet of FIG. 1, the control gate electrode CG is integrallyformed in common with one another. Moreover, as similar to the controlgate electrode CG, in the plurality (for example, several tens toseveral hundreds) of memory cells MC, the memory gate electrode MG isintegrally formed in common with one another. In other words, in orderto achieve the high-speed operations of the nonvolatile memory, it isimportant to achieve the low resistances of the control gate electrodeCG and the memory gate electrode MG.

The control gate electrode CG and the memory gate electrode MG areadjacent to each other via the gate insulating film GIm therebetween,and the memory gate electrode MG is formed in a sidewall spacer form onthe side surfaces, that is, the sidewalls of the control gate electrodeCG via the gate insulating film GIm. Moreover, the gate insulating filmGIm is extended over a region between the memory gate electrode MG andthe semiconductor substrate SB and a region between the memory gateelectrode MG and the control gate electrode CG.

The gate insulating film GIt is made of an insulating film IF1. Theinsulating film IF1 is made of a silicon oxide film, a silicon nitridefilm, an oxynitride silicon film, or a high dielectric constant filmhaving a dielectric constant (relative permittivity) higher than that ofthe silicon nitride film, that is, a so-called High-k film. In thepresent embodiment, when the High-k film or the high dielectric constantfilm is described, note that this means a film having a dielectricconstant (relative permittivity) higher than that of the silicon nitridefilm. As the insulating film IF1, for example, a metal oxide film suchas a hafnium oxide film, a zirconium oxide film, an aluminum oxide film,a tantalum oxide film or a lanthanum oxide film can be used.

The gate insulating film GIm is made of an insulating film ON. Theinsulating film ON is configured by a stacked film including a siliconoxide film OX1, a silicon nitride film NT formed on the silicon oxidefilm OX1 and a silicon oxide film OX2 formed on the silicon nitride filmNT. The gate insulating film GIm located between the memory gateelectrode MG and the control gate electrode CG functions as aninsulating film for insulating a gap between the memory gate electrodeMG and the control gate electrode CG, that is, for electricallyisolating these electrodes from each other. Therefore, the insulatingfilm between the memory gate electrode MG and the control gate electrodeCG may be formed as an insulating film that is separated or differentfrom the insulating film between the memory gate electrode MG and thesemiconductor substrate SB.

The silicon nitride film NT of the insulating films ON is an insulatingfilm for storing charges, and functions as a charge storage portion.That is, the silicon nitride film NT is a trapping insulating filmformed in the insulating film ON. For this reason, the insulating filmON can be regarded as an insulating film having a charge storage portiontherein.

The silicon oxide film OX1 and the silicon oxide film OX2 located on theupper and lower sides of the silicon nitride film NT are allowed tofunction as charge block layers for trapping the charges inside. Thatis, by providing a configuration in which the silicon nitride film NT issandwiched by the silicon oxide film OX1 and the silicon oxide film OX2,leakage of the charges stored in the silicon nitride film NT can beprevented.

The control gate electrode CG is made of a silicon film PS1. The siliconfilm PS1 is made of silicon, and is made of, for example, an n-typepolysilicon film or others serving as a polycrystal silicon film towhich an n-type impurity is introduced. More specifically, the controlgate electrode CG is made of a patterned silicon film PS1. On the uppersurface of the silicon film PS1 forming the control gate electrode CG, asilicide layer S2 is formed. The silicide layer S2 is also extended in adirection perpendicular to the surface sheet of FIG. 1 as similar to thecontrol gate electrode CG.

The memory gate electrode MG is made of a silicon film PS2. The siliconfilm PS2 is made of silicon, and is made of, for example, a p-typepolysilicon film or others serving as a polycrystal silicon film towhich a p-type impurity is introduced. The memory gate electrode MG isformed in a sidewall spacer form on one sidewall of the control gateelectrode CG adjacent to this memory gate electrode MG via the gateinsulating film GIm. On the upper surface of the silicon film PS2forming the memory gate electrode MG, a silicide layer S2 is formed. Thesilicide layer S2 is also extended in a direction perpendicular to thesurface sheet of FIG. 1 as similar to the memory gate electrode MG.

FIG. 1 separately shows the control gate electrode CG and the silicidelayer S2. However, they are sometimes referred to as control gateelectrode so as to include the silicide layer S2. A relation between thememory gate electrode MG and the silicide layer S2 is similarlydescribed.

The silicide layer S2 formed on each upper surface of the control gateelectrode CG and the memory gate electrode MG is an alloy layer ofnickel (Ni) and silicon (Si) containing platinum (Pt) as an additive.The content (content rate) of platinum is preferably less than 5%(including 0%). Although described in detail later, by reducing thecontent of platinum in the silicide layer S2, increase in the sheetresistance of the control gate electrode CG and the memory gateelectrode MG can be prevented.

The extension region EX and the diffusion region DF are semiconductorregions functioning as a source region or a drain region. Each of theextension region EX and the diffusion region DF is made of asemiconductor region to which an n-type impurity is introduced, and bothof them form an LDD (Lightly doped drain) structure. The diffusionregion DF has a concentration higher than that of the extension regionEX, and also has a large junction depth relative to the well region PW1.The paired extension region EX and the diffusion region DF are disposedon both ends of the control gate electrode CG and the memory gateelectrode MG so as to sandwich the control gate electrode CG and thememory gate electrode MG therebetween. However, the extension regions EXare disposed between one of the diffusion regions DF and the controlgate electrode CG and between the other diffusion region DF and thememory gate electrode MG.

A silicide layer S1 is formed on the diffusion region DF, that is, onthe upper surface (surface) of the diffusion region DF. The silicidelayer S1 formed on the upper surface of the diffusion region DF is analloy layer of nickel (Ni) and silicon (Si) that contains platinum (Pt)as an additive. The content (content rate) of the platinum (Pt) is 5% ormore (more preferably, 5% or more and 10% or less). By setting thecontent of platinum (Pt) serving as an additive to 5% or more, abnormalgrowth of the silicide layer S1 is suppressed, so that a leak current inthe source region or the drain region can be reduced. Moreover, bysetting the content of platinum (Pt) to 10% or less, an unreactedportion of the nickel (Ni) film containing platinum (Pt) can be easilyremoved in a manufacturing method to be described later. Note that aregion including the extension region EX, the diffusion region DF andthe silicide layer S1 is sometimes represented as the source region orthe drain region.

In place of the nickel silicide layer containing an additive, each ofthe silicide layers S1 and S2 may be a cobalt silicide layer containingthe additive, and the additive may be aluminum (Al) or carbon (C).

On the sidewalls of the control gate electrode CG and the sidewalls ofthe memory gate electrode MG, a sidewall spacer SW made of an insulatingfilm such as a silicon oxide film, a silicon nitride film or a stackedfilm of these films is formed.

Next, the configuration of an n-channel-type low breakdown voltageMISFET (Q1) formed in the peripheral circuit region 1B will bedescribed.

In the peripheral circuit region 1B, the semiconductor device has anactive region and an element isolation region ST formed on the mainsurface of the semiconductor substrate SB. The structure and thefunctions of the element isolation region ST are as described above. Theactive region is defined, that is, partitioned by the element isolationregion ST, is electrically isolated from other active region in theperipheral circuit region 1B by the element isolation region ST, and ap-type well PW2 having a p-conductivity type is formed in the activeregion. The p-type well PW1 in the memory cell region 1A is surroundedby an n-type well not shown, and is electrically isolated from thep-type well PW2. That is, a potential different from that of the p-typewell PW2 can be applied to the p-type well PW1.

As shown in FIG. 1, the low breakdown voltage MISFET (Q1), which isformed in the peripheral circuit region 1B, has an n-type extensionregion (n⁻-type semiconductor region, low concentration region, impuritydiffusion region) EX and an n-type diffusion region (n⁺-typesemiconductor region, high concentration region, impurity diffusionregion) DF that are formed inside the p-type well PW2 and serve as thegate electrode G1 and the source region or the drain region. Moreover,the low breakdown voltage MISFET (Q1) has the silicide layer (SDsilicide layer) S1 formed on the upper surface of the diffusion regionDF. The silicide layer (SD silicide layer) S1 has the same compositionas the silicide layer S1 formed in the source region and the drainregion of the memory cell MC. However, on the upper surface of the gateelectrode G1, no silicide layer S2 is formed. Moreover, the lowbreakdown voltage MISFET (Q1) has a gate insulating film GIL formedbetween the gate electrode G1 and the semiconductor substrate SB (orp-type well PS2).

The gate insulating film GIL has a stacked structure configured by aninsulating film IF4 and an insulating film HK formed on the insulatingfilm IF4. The insulating film IF4 is, for example, a silicon oxide film,and the insulating film HK is, for example, an insulating material filmhaving a dielectric constant (relative permittivity) higher than thoseof silicon oxide and silicon nitride, which is a so-called high-k film(high dielectric constant film). As the insulating film HK, a metaloxide film such as a hafnium oxide (HfO) film, a zirconium oxide (ZrO)film, an aluminum oxide (AlO) film, a tantalum oxide (TaO) film or alanthanum oxide (LaO) film may be used. For example, the hafnium oxide(HfO) film is a film containing hafnium (Hf) and oxygen (O), and itscomposition ratio is not particularly limited. The same goes for thezirconium oxide (ZrO) film, the aluminum oxide (AlO) film, the tantalumoxide (TaO) film or the lanthanum oxide (LaO) film.

On the gate insulating film GIL, a gate electrode G1 is formed via ametal film TN. The metal film TN is a film for use in adjusting thethreshold voltage of the low breakdown voltage MISFET (Q1). As the metalfilm TN, for example, a titanium nitride (TiN) film, a tantalum nitride(TaN) film, a tungsten nitride (WN) film, a titanium carbide (TiC) film,a tantalum carbide (TaC) film, a tungsten carbide (WC) film, a tantalumcarbide nitride (TaCN) film, a titanium (Ti) film, a tantalum (Ta) film,a titanium aluminum (TiAl) film, an aluminum (Al) film or others can beused.

The gate electrode G1 is made of a metal film. The metal film means aconductive film having metal conductivity, and is not only a singlemetal film (pure metal film) or an alloy film but also includes a metalcompound film having metal conductivity. As a preferable example, atitanium aluminum (TiAl) film can selected as the metal film TN, and analuminum (Al) film can be selected as the gate electrode G1 on the metalfilm TN.

The extension region EX and the diffusion region DF are semiconductorregions functioning as a source region or a drain region. Each of theextension region EX and the diffusion region DF is made of asemiconductor region to which an n-type impurity is introduced, and bothof them form an LDD structure. The diffusion region DF has aconcentration higher than that of the extension region EX, and also hasa large junction depth relative to the well region PW2. The pairedextension region EX and the diffusion region

DF are disposed on both ends of the gate electrode G1 so as to sandwichthe gate electrode G1 therebetween. However, the extension regions EXare disposed between one of the diffusion regions DF and the gateelectrode G1 and between the other diffusion region DF and the gateelectrode G1.

The above-described silicide layer S1 is formed on the diffusion regionDF, that is, on the upper surface (surface) of the diffusion region DF.On the sidewalls of the gate electrode G1, a sidewall spacer SW made ofan insulating film such as a silicon oxide film, a silicon nitride filmor a stacked film of these films is formed. Note that they are sometimesreferred to as the source region or the drain region so as to includethe extension region EX, the diffusion region DF and the silicide layerS1.

Next, the configuration of an n-channel-type high breakdown voltageMISFET (Q2) formed in the peripheral circuit region 1C will bedescribed.

In the peripheral circuit region 1C, the semiconductor device has anactive region and an element isolation region ST formed on the mainsurface of the semiconductor substrate SB. The structure and thefunctions of the element isolation region ST are as described above. Theactive region is defined, that is, partitioned by the element isolationregion ST, is electrically isolated from other active region in theperipheral circuit region 1C by the element isolation region ST, and ap-type well PW3 having a p-conductivity type is formed in the activeregion. As described above, the p-type well PW1 is surrounded by ann-type well not shown, and therefore, is electrically isolated from thep-type well PW3. That is, a potential different from that of the p-typewell PW3 can be applied to the p-type well PW1.

As shown in FIG. 1, the high breakdown voltage MISFET (Q2), which isformed in the peripheral circuit region 1C, has an n-type extensionregion (n³¹-type semiconductor region, low concentration region,impurity diffusion region) EX and an n-type diffusion region (n⁺-typesemiconductor region, high concentration region, impurity diffusionregion) DF that are formed inside the p-type well PW3 and serve as thegate electrode G2 and the source region or the drain region. Moreover,the high breakdown voltage MISFET (Q2) has the silicide layer (SDsilicide layer) S1 formed on the upper surface of the diffusion regionDF, and has the silicide layer (gate silicide layer) S2 formed on theupper surface of the gate electrode G2. The silicide layers S1 and S2are the same as the above-described silicide layers S1 and S2.

Furthermore, the high breakdown voltage MISFET (Q2) has agate insulatingfilm GIH formed between the gate electrode G2 and the semiconductorsubstrate SB (or p-type well PW3).

More preferably, by making the gate length of the gate electrode G2 ofthe high breakdown voltage MISFET (Q2) to be larger (longer) than thegate length of the gate electrode G1 of the low breakdown voltage MISFET(Q1), the breakdown voltage between the source region and the drainregion can be improved. Note that the gate length means a length of thegate electrode in a direction connecting the source region and the drainregion with each other. That is, the length is the length of the gateelectrode in a lateral direction of the drawing sheet of FIG. 1.

The gate insulating film GIH is made of an insulating film IF1. Theinsulating film IF1 is made of a silicon oxide film, a silicon nitridefilm or a silicon oxynitride film, and more preferably, is thicker thanthe gate insulating film GIt. Moreover, a thickness of the insulatingfilm IF1 is preferably larger than that of the gate insulating film GILof the low breakdown voltage MISFET (Q1) in equivalent oxide thickness,and more preferably, thicker than at least the insulating film IF4.

A gate electrode G2 is disposed on the gate insulating film GIH, and thegate electrode G2 is made of the above-described silicon film PS1.Moreover, on the upper surface of the gate electrode G2, theabove-described silicide layer S2 is formed.

The source region and drain region of the high breakdown voltage MISFET(Q2) have the LDD structure configured by an extension region EX and adiffusion region DF as similar to the low breakdown voltage MISFET (Q1).However, more preferably, the impurity concentration of the extensionregion EX of the high breakdown voltage MISFET (Q2) may be lower thanthe impurity concentration of the extension region EX of the lowbreakdown voltage MISFET (Q1).

The silicide layer S1 formed on the upper surface of the diffusionregion DF of the high breakdown voltage MISFET (Q2) is the same as thesilicide layer S1 formed on the upper surface of the diffusion region DFof the low breakdown voltage MISFET (Q1) and the memory cell MC.Moreover, the silicide layer S2 formed on the upper surface of the gateelectrode G2 of the high breakdown voltage MISFET (Q2) is the same asthe silicide layer S2 formed on the upper surface of the control gateelectrode CG and the memory gate electrode MG of the memory cell MC.

Moreover, in the present embodiment, since the channel direction (thatis, a direction from the source region toward the drain region) of thehigh breakdown voltage MISFET (Q2) is set to a <110> or <100> direction,whisker defects which expands the silicide layer S1 formed on the uppersurface of the diffusion region DF in the channel direction tends toeasily occur. However, since platinum (Pt) is contained in the silicidelayer S1, the occurrence of the whisker defects can be prevented.

On the sidewalls of the gate electrode G2, a sidewall spacer SW made ofan insulating film such as a silicon oxide film, a silicon nitride filmor a stacked film of these films is formed. Note that they are sometimesreferred to as the source region or the drain region so as to includethe extension region EX, the diffusion region DF and the silicide layerS1.

Next, configurations on the memory cell MC formed in the memory cellregion 1A, on the low breakdown voltage MISFET (Q1) formed in theperipheral circuit region 1B and on the high breakdown voltage MISFET(Q2) formed in the peripheral circuit region 1C, will be specificallyexplained.

On the semiconductor substrate SB, a stacked film of an insulating filmIF7 and an interlayer insulating film IL1 is formed so as to fill gapsbetween the control gate electrode CG and the memory gate electrode MGof the memory cell MC and between the gate electrode G1 of the lowbreakdown voltage MISFET (Q1) and the gate electrode G2 of the highbreakdown voltage MISFET (Q2). Based on the main surface of thesemiconductor substrate SB as a reference, the upper surface of thestacked film of the insulating film IF7 and the interlayer insulatingfilm IL1 has almost the same height as the upper surfaces of the controlgate electrode CG, the memory gate electrode MG and the gate electrodesG1 and G2. The insulating film IF7 is made of, for example, a siliconnitride film, and the interlayer insulating film IL1 is made of, forexample, a silicon oxide film.

On the interlayer insulating film IL1, an interlayer insulating film IL2made of, for example, a silicon oxide film is formed. In the peripheralcircuit region 1B, an insulating film IF9 made of a silicon oxide filmis interposed between the interlayer insulating film IL1 and theinterlayer insulating film IL2.

In the memory cell region 1A and the peripheral circuit regions 1B and1C, contact holes each of which exposes, for example, a part of thesilicide layer S1 on the surface of the diffusion region DF are formedin the insulating film IF7, the interlayer insulating film IL1 and theinterlayer insulating film IL2, and a conductive contact plug CP isformed inside each of the contact holes. The contact plug CP isconfigured by a main conductor made of tungsten (W) or others and abarrier conductor film (for example, a titanium film, a titanium nitridefilm or a stacked film of these films), and the barrier conductor filmis interposed between the main conductor and the silicide layer S1.Moreover, in the peripheral circuit region 1B, the contact hole alsopenetrates the insulating film IF9.

A wiring layer M1 serving as a first layer is disposed on each of thecontact plugs CP, and the wiring layer M1 is connected to the silicidelayer S1 via the contact plug CP. That is, the wiring layer M1 iselectrically connected to the diffusion region DF. The wiring layer M1is formed by a conductor film containing, for example, aluminum (Al) orcopper (Cu) as a main conductor.

<Characteristics and Effects of Semiconductor Device of PresentEmbodiment>

In the present embodiment, it is important to make a concentration(content) of an additive contained in the silicide layer S1 formed onthe upper surface of the diffusion region DF to be higher than aconcentration (content) of an additive contained in the silicide layerS2 formed on the upper surfaces of the control gate electrode CG, thememory gate electrode MG and the gate electrode G2. By making theconcentration of the additive contained in the silicide layer S1 to behigher, the abnormal growth of the silicide layer S1 to be formed on theupper surface of the diffusion region DF can be prevented, so that aleak current between the source region or the drain region and the wellregions PW1, PW2 and PW3 can be reduced. In other words, this iseffective for reducing the power consumption of the semiconductordevice.

If the additive having the same concentration as that of the silicidelayer S1 is contained in the silicide layer S2, the resistance of thegate electrode including the silicide layer S2 is increased by theincrease in the sheet resistance of the silicide layer S2, andtherefore, the high-speed operation is prevented. Since crystal grainsof a silicide layer having a high additive concentration areminiaturized, a possibility of grain-boundary scattering of the electriccurrent (electrons) flowing through the silicide layer becomes higher.Moreover, because the additive is contained, the possibility of theelectron scattering becomes higher. It is considered that the sheetresistance of the silicide layer is increased because of these factors.In other words, in the present embodiment, since the concentration ofthe additive contained in the silicide layer S2 is lower than theconcentration of the additive contained in the silicide layer S1, thecrystal grain size of the silicide layer S2 can be made larger than thecrystal grain size of the silicide layer S1. This manner has such afeature as reducing the sheet resistance of the silicide layer S2. Thatis, this manner is effective for operating the MISFET at the high speedbecause of the reduction of the resistance of the gate electrode of theMISFET.

According to the present embodiment, by reducing the concentration ofthe additive in the silicide layer S2 to be lower than the concentrationof the additive in the silicide layer S1, the sheet resistance of thesilicide layer S2 can be reduced. Particularly, the control gateelectrode CG or the memory gate electrode MG of the memory cell MC isalso used as a common wiring for a plurality of memory cells MC, andtherefore, the length of each of the control gate electrode CG and thememory gate electrode MG in the gate width direction becomes longer thanthat of the low breakdown voltage MISFET (Q1) formed in the peripheralcircuit region 1B. For this reason, the reduction in the resistance ofthe silicide layer S2 on the upper surface of the control gate electrodeCG or the memory gate electrode MG is effective for operating thenonvolatile memory at the high speed.

Here, the concentration of the additive contained in each of thesilicide layers S1 and S2 means, for example, a concentration thereofper unit area of the surface of each of the silicide layers S1 and S2.Moreover, relative comparison in a content rate between the first metal(for example, Ni) and the second metal (for example, Pt) that is anadditive contained in the silicide layers S1 and S2 containing siliconcan be made by, for example, an energy dispersive X-ray spectroscopy(EDX) method. For example, the element analysis and composition analysisof the silicide layers S1 and S2 can be executed by detecting thecharacteristic X-ray caused by irradiating the surface (upper surface)of each of the silicide layers S1 and S2 with an electron beam, andperforming the spectroscopy based on energy.

In the present embodiment, each of the control gate electrode CG and thememory gate electrode MG forming the memory cell MC is configured by apolysilicon film and a silicide layer S2 formed on the surface (uppersurface) of the polysilicon film, and the control gate electrode CG andthe memory gate electrode MG are isolated from each other by a gateinsulating film GIm. By forming such a configuration, the wiringresistance of the control gate electrode CG and the memory gateelectrode MG can be reduced without short-circuit between the controlgate electrode CG and the memory gate electrode MG. For example, whenthe technique of full silicide gate of Patent Document 2 is applied tothe control gate electrode CG and memory gate electrode MG, there is aproblem of the short circuit between the control gate electrode CG andthe memory gate electrode MG in the silicidation process of the controlgate electrode CG and the memory gate electrode MG. That is, it isdifficult to apply the technique of the full silicide gate of PatentDocument 2 to the split gate type nonvolatile memory of the presentembodiment.

<Method for Manufacturing Semiconductor Device>

A method for manufacturing the semiconductor device of the presentembodiment will be described with reference to FIGS. 2 to 20.

FIGS. 2 to 20 are cross-sectional views during manufacturing processesof the semiconductor device of the present embodiment. Eachcross-sectional view of FIGS. 2 to 20 corresponds to the cross-sectionalview of FIG. 1. The memory cell region 1A is shown on the left side ineach of the drawings, the peripheral circuit region 1B is shown at thecenter therein, and the peripheral circuit region 1C is shown on theright side therein. The drawings show the formation of the memory cellMC of the nonvolatile memory in the memory cell region 1A and theformation of the low breakdown voltage MISFET (Q1) and the highbreakdown voltage MISFET (Q2) in the peripheral circuit regions 1B and1C, respectively.

In the manufacturing processes of the semiconductor device, first, asemiconductor substrate (semiconductor wafer) SB made of a p-type singlecrystal silicon (Si) or others is prepared as shown in FIG. 2. Then, onthe main surface of the semiconductor substrate SB, a plurality ofelement isolation regions ST for defining the active regions are formed.

Each of the element isolation regions ST is made of an insulator such assilicon oxide, and can be formed by using, for example, an STI method,an LOCOS method or others. Here, the formation of the element isolationregions by using the STI method will be described.

In other words, after stacking a silicon oxide film and a siliconnitride film on the semiconductor substrate SB in this order, thesilicon nitride film and the silicon oxide film are etched by using aphotolithography technique and a dry etching method so that patternedsilicon nitride film and silicon oxide film that selectively cover theactive regions are formed. Moreover, trenches are formed on the uppersurface of the semiconductor substrate SB exposed from the patternedsilicon nitride film and silicon oxide film. A plurality of the trenchesare formed.

Subsequently, after burying an insulating film made of, for example,silicon oxide into the trenches, the respective insulating films on thesilicon nitride film are removed by a polishing process or others, sothat a plurality of element isolation regions ST are formed. The elementisolation regions ST are formed so as to surround the active region, andare formed among the memory cell region 1A, the peripheral circuitregion 1B and the peripheral circuit region 1C. Thus, a configurationshown in FIG. 2 is obtained.

Next, p-type wells PW1, PW2 and PW3 are formed on the main surface ofthe semiconductor substrate SB in the memory cell region 1A, theperipheral circuit region 1B and the peripheral circuit region 1C. Thep-type wells PW1, PW2 and PW3 can be formed by ion-implanting a p-typeimpurity such as boron (B) to the semiconductor substrate SB. Note thatthe p-type wells PW1, PW2 and PW3 to be formed in the respectiveformation regions of the memory cell MC, the high breakdown voltageMISFET (Q2), the low breakdown voltage MISFET (Q1) or others can beformed by using the same ion-implanting process. However, for optimizingthe characteristics of the respective elements, they can be also formedin the respective regions by using different ion-implanting processes.For example, the concentration of the p-type well PW3 in the peripheralcircuit region 1C is preferably set to be higher than the concentrationof the p-type well PW2 in the peripheral circuit region 1B.

Next, as shown in FIG. 2, on the main surface of the semiconductorsubstrate SB, an insulating film IF1 for the gate insulating film isformed. That is, the insulating film IF1 is formed on the upper surface(surface) of the semiconductor substrate SB in the memory cell region 1Aand the peripheral circuit regions 1B and 1C. As the insulating filmIF1, for example, a silicon oxide film can be used. The respectiveinsulating films IF1 in the memory cell region 1A and the peripheralcircuit regions 1B and 1C may be formed by using different processesfrom each other so as to have different film thicknesses. Morepreferably, the insulating film IF1 in the peripheral circuit region 1Cis made thicker than the insulating film IF1 in the memory cell region1A.

Then, a silicon film PS1 made of a polycrystal silicon film is formed onthe semiconductor substrate SB by using, for example, a CVD (ChemicalVapor Deposition) method so as to cover the upper surface of theinsulating film IF1. Moreover, the silicon film PS1 can be formed as alow-resistance semiconductor film (a doped polysilicon film) byintroducing an impurity at the time of film formation, by ion-implantingan impurity after the film formation, or by others. As the n-typeimpurity to be introduced into the silicon film PS1, for example,phosphorus (P) can be preferably used.

Then, on the silicon film PS1, an insulating film IF2 is formed byusing, for example, a CVD method. The insulating film IF2 is a capinsulating film made of, for example, silicon nitride (SiN). The filmthickness of the insulating film IF2 can be set in a range of, forexample, about 20 to 50 nm.

Next, as shown in FIG. 3, the stacked film, made of the insulating filmIF2, the silicon film PS1 and the insulating film IF1 in the memory cellregion 1A, is patterned by using a photolithography technique and anetching technique. Thus, in the memory cell region 1A, a stacked body ofa gate insulating film GIt made of the insulating film IF1, a controlgate electrode CG made of the silicon film PS1 and a cap insulating filmmade of the insulating film IF2 is formed. In a plan view, the controlgate electrode CG forms a pattern extending in a gate width direction.The gate width direction corresponds to a depth direction of the drawingsheet of FIG. 3.

In the above-described patterning process, the stacked film made of theinsulating film IF2, the silicon film PS1 and the insulating film IF1 isprocessed also between the peripheral circuit regions 1B and 1C by usingthe photolithography technique and the etching technique. In otherwords, between the peripheral circuit regions 1B and 1C, the stackedbodies each made of the insulating film IF2, the silicon film PS1 andthe insulating film IF1 are separated from one another, and is alsoseparated from the stacked body made of the insulating film IF2, thesilicon film PS1 and the insulating film IF1 in the memory cell region1A. However, it is not always required to separate the insulating filmIF1.

Next, as shown in FIG. 3, by using a photolithography technique and awet etching method that are different from the patterning process of theabove-described stacked film, the insulating film IF2 in the peripheralcircuit region 1B is selectively removed. Thus, the upper surface of thesilicon film PS1 in the peripheral circuit region 1B is exposed. At thisstage, the insulating films IF2 in the memory cell region 1A and theperipheral circuit region 1C are not removed but left. That is, theabove-described wet-etching process is performed by using, as a mask, aresist film having a pattern that covers the memory cell region 1A andthe peripheral circuit region 1C and exposes the peripheral circuitregion 1B although not shown, so that the resist film not shown isremoved after the above-described wet etching process.

Then, as shown in FIG. 4, an insulating film ON for forming theabove-described gate insulating film GIm is formed on the main surfaceof the semiconductor substrate SB. The insulating film ON covers theupper surface of the semiconductor substrate SB in the memory cellregion 1A and the sidewalls and the upper surface of a stacked body madeof the gate insulating film GIt, the control gate electrode CG and theinsulating film IF2. Moreover, it also covers the sidewalls and theupper surface of the stacked body including the insulating film IF1 andthe silicon film PS1 in the peripheral circuit region 1B, and furthercovers the sidewalls and the upper surface of the stacked body includingthe insulating film IF1, the silicon film PS1 and the insulating filmIF2 in the peripheral circuit region 1C.

The insulating film ON is an insulating film having a charge storageportion therein. More specifically, the insulating film ON is made of astacked film configured by a silicon oxide film OX1 formed on thesemiconductor substrate SB, a silicon nitride film NT formed on thesilicon oxide film OX1 and a silicon oxide film OX2 formed on thesilicon nitride film NT.

The silicon oxide films OX1 and OX2 can be formed by, for example, anoxidation treatment (thermal oxidation treatment), a CVD method, or acombination of them. Particularly, for forming the silicon oxide filmOX2, an ISSG (In-Situ Steam Generation) oxidation treatment can be alsoused. The silicon nitride film NT can be formed by, for example, a CVDmethod.

In the present embodiment, the memory cell is formed, and the siliconnitride film NT is formed as an insulating film (charge storage layer)having a trap level. As a film used for the charge storage layer, asilicon nitride film is preferable from the viewpoint of reliability orothers. However, the film is not limited to the silicon nitride film,and a high dielectric constant film (high dielectric constant insulatingfilm) such as an aluminum oxide film (alumina), a hafnium oxide film, atantalum oxide film having a dielectric constant higher than that of thesilicon nitride film maybe used as the charge storage layer or thecharge storage portion.

The thickness of the silicon oxide film OX1 can be set in a range of,for example, about 2 to 10 nm, the thickness of the silicon nitride filmNT can be set in a range of, for example, about 5 to 15 nm, and thethickness of the silicon oxide film OX2 can be set in a range of, forexample, about 2 to 10 nm.

Subsequently, a polycrystal silicon film PS2 is formed on the mainsurface of the semiconductor substrate SB so as to cover the surface ofthe insulating film ON by using, for example, a CVD method. Thus, theupper surface of the insulating film ON in the memory cell region 1A iscovered with the silicon film PS2. That is, on the sidewalls of thecontrol gate electrode CG, the silicon film PS2 is formed via theinsulating film ON.

The film thickness of the silicon film PS2 is, for example, 40 nm. Afterthe silicon film PS2 is formed as an amorphous silicon film at the timeof the film formation, this silicon film PS2 can be changed to thesilicon film PS2 made of a polycrystal silicon film by a subsequentthermal treatment. The silicon film PS2 is a film to which, for example,a p-type impurity (for example, boron (B)) is introduced at acomparatively high concentration. The silicon film PS2 is a film for usein forming the memory gate electrode MG.

The film thickness described here means a thickness of the film in adirection perpendicular to the main surface of the semiconductorsubstrate SB.

Note that FIG. 4 shows the insulating film ON having a stacked layerstructure of three layers formed of the silicon oxide film OX1, thesilicon nitride film NT and the silicon nitride film NT. However, in across-sectional view used for the following explanation, theillustration of the stacked layer structure of the insulating film ON isomitted in order to easily understand the drawing. That is, although theinsulating film ON has the stacked layer structure, the insulating filmON is illustrated as a single film GIm in the drawings used for thefollowing explanation.

Next, by etching back (anisotropically dry-etching) the silicon film PS2by an anisotropic etching technique, the upper surface of the insulatingfilm ON is selectively exposed. In this etching back process, byanisotropically etching (etching back) the silicon film PS2, the siliconfilm PS2 is left in a sidewall shape via the insulating film ON on bothof sidewalls of the stacked body made of the gate insulating film GIt,the control gate electrode CG and the insulating film IF2.

Thus, in the memory cell region 1A, a memory gate electrode MG made ofthe sidewall-shaped silicon film PS2 that is left via the insulatingfilm ON is formed on one sidewall of the sidewalls of theabove-described stacked body. Moreover, by the above-described etchingback process, the upper surface of the insulating film ON in each of theperipheral circuit regions 1B and 1C is exposed.

Subsequently, by using a photolithography technique, a resist film (notshown) is formed on the semiconductor substrate SB so as to cover thememory gate electrode MG adjacent to one sidewall of the control gateelectrode CG and so as to expose the silicon film PS2 adjacent to theother sidewall of the control gate electrode CG. Then, by performing anetching process while using the resist film as an etching mask, thesilicon film PS2 formed on the opposite side of the memory gateelectrode MG across the control gate electrode CG is removed. Then, theresist film is removed. In this etching process, the memory gateelectrode MG is covered with the resist film, and therefore, is notetched but left.

Subsequently, a part of the insulating film ON, the part being notcovered with the memory gate electrode MG but exposed, is removed byetching (for example, wet etching). At this stage, in the memory cellregion 1A, the insulating film ON right below the memory gate electrodeMG is not removed but left. Similarly, the insulating film ON locatedbetween the memory gate electrode MG and the stacked body including thegate insulating film GIt, the control gate electrode CG and theinsulating film IF2 is not removed but left.

Since the insulating films ON in the other regions are removed, theupper surface of the semiconductor substrate SB and the upper surface ofthe insulating film IF2 in the memory cell region 1A are exposed, andthe upper surface of the silicon film PS1 in the peripheral circuitregion 1B and the upper surface of the insulating film IF2 in theperipheral circuit region 1C are further exposed. Moreover, one sidewallof the sidewalls of the control gate electrode CG, the sidewall beingnot adjacent to the memory gate electrode MG, is exposed.

In this manner, as shown in FIG. 5, the gate insulating film GIm made ofthe insulating film ON having the charge storage portion therein and thememory gate electrode MG on the gate insulating film GIm are formed onthe semiconductor substrate SB so as to be adjacent to the control gateelectrode CG.

Next, on the main surface of the semiconductor substrate SB, aninsulating film IF3 is formed by using, for example, a CVD method. Theinsulating film IF3 is made of, for example, a silicon nitride film.Thus, the silicon film PS1 in the peripheral circuit region 1B and thesilicon film PS1 and the insulating film IF2 in the peripheral circuitregion 1C are covered with the insulating film IF3. Moreover, thestacked body made of the gate insulating film GIt in the memory cellregion 1A, the control gate electrode CG and the insulating film IF2,the gate insulating film GIm and the memory gate electrode MG adjacentto the sidewalls of the stacked body, and the main surface of thesemiconductor substrate SB in the memory cell region 1A are covered withthe insulating film IF3. Note that the insulating film IF3 may be formedas a stacked film of a silicon oxide film and a silicon nitride film onthe silicon oxide film.

Subsequently, as shown in FIG. 6, by using a photolithography technique,the peripheral circuit region 1C is exposed, and a resist film PR1 thatcovers the insulating films IF3 in the memory cell region 1A and theperipheral circuit region 1C is formed. In the peripheral circuit region1B, note that each insulating film IF3 adjacent to the upper surface andthe sidewalls of the silicon film PS1 is exposed from the resist filmPR1.

Next, the insulating film IF3 exposed from the resist film PR1 isremoved by a wet etching method, and then, the resist film PR1 isremoved. Thus, the silicon film PS1 in the peripheral circuit region 1Bis exposed.

Then, as shown in FIG. 7, the main surface of the semiconductorsubstrate SB is exposed by removing the silicon film PS1 and theinsulating film IF1 in the peripheral circuit region 1B by using, forexample, a wet etching method while using the insulating film IF3 as amask. At this stage, the stacked body configured by the gate insulatingfilm GIt, the control gate electrode CG and the insulating film IF2, andthe gate insulating film GIm in the memory cell region 1A and the memorygate electrode MG that are adjacent to the sidewalls of the stacked bodyare covered with the insulating film IF3, and therefore, are notremoved. Moreover, the insulating film IF2, the silicon film PS1 and theinsulating film IF1 in the peripheral circuit region 1C are covered withthe insulating film IF3, and therefore, are not removed.

Next, as shown in FIG. 8, insulating films IF4 and HK, a metal film TN,a silicon film PS3 and an insulating film IF5 are sequentially formed onthe main surface of the semiconductor substrate SB. However, theinsulating film IF4 is made of, for example, a silicon oxide film, andis formed by using an oxidizing method such as a thermal oxidizingmethod, and therefore, the insulating film IF4 is formed only on themain surface of the semiconductor substrate SB in the peripheral circuitregion 1B. Thus, the stacked body configured by the gate insulating filmGIt, the control gate electrode CG and the insulating film IF2 in thememory cell region 1A, and the gate insulating film GIm and the memorygate electrode MG that are adjacent to the sidewalls of the stackedbody, are also covered with the insulating films IF3 and HK, the metalfilm TN, the silicon film PS3 and the insulating film IF5. Moreover, thestacked body configured by the insulating film IF1, the silicon film PS1and the insulating film IF2 in the peripheral circuit region 1C are alsocovered with the insulating films IF3 and HK, the metal film TN, thesilicon film PS3 and the insulating film IF5.

The insulating film HK is an insulating film for the gate insulatingfilm. More specifically, the insulating film IF4 and the insulating filmHK are films that configure the gate insulating film of the MISFET (Q1)to be formed later in the peripheral circuit region 1B. The insulatingfilm HK is an insulating film having a dielectric constant (relativedielectric constant) higher than those of silicon oxide and siliconnitride, that is so called high-k film (high dielectric constant film).

As the insulating film HK, a metal oxide film such as a hafnium oxidefilm, a zirconium oxide film, an aluminum oxide film, a tantalum oxidefilm, a lanthanum oxide film or others, can be used, and these metaloxide films can further contain either one or both of nitrogen (N) andsilicon (Si). The insulating film HK can be formed by, for example, anALD (Atomic Layer Deposition) method or others. The film thickness ofthe insulating film HK is, for example, 1.5 nm. In the case of usage ofthe high dielectric constant film (here, the insulating film HK) as thegate insulating film, the physical film thickness of the gate insulatingfilm can be larger than the case of the usage of the silicon oxide film,and therefore, the case can obtain such an advantage as reducing a leakcurrent.

The metal film TN is made of, for example, a titanium nitride film, andcan be formed by using, for example, a sputtering method. The siliconfilm PS3 is made of a polysilicon film, and can be formed by using, forexample, a CVD method. The film thickness of the silicon film PS3 is,for example, 40 nm. After the silicon film PS3 is formed as an amorphoussilicon film at the time of the film formation, this silicon film PS3made of the amorphous silicon film can be also changed to the siliconfilm PS3 made of a polycrystal silicon film by a subsequent thermaltreatment. The silicon film PS3 is a film for use in forming a dummygate electrode DG described later. The insulating film IF5 is a capinsulating film made of, for example, silicon nitride, and can be formedby using, for example, a CVD method.

Next, as shown in FIG. 9, insulating films IF4 and HK, a metal film TN,a silicon film PS3 and an insulating film IF5 are selectively left inthe peripheral circuit region 1B. And, the insulating film IF4 and HK,the metal film TN, the silicon film PS3 and the insulating film IF5 areremoved from the memory cell region 1A and the peripheral circuit region1C by, for example, a wet etching method. In this wet etching method,the wet etching method is performed by selectively covering an uppersurface of a stacked body configured by the insulating films IF4 and HK,a metal film TN, a silicon film PS3 and an insulating film IF5 in theperipheral circuit region 1B with an insulating film such as a siliconoxide film, and then, by using this insulating film as a mask.

Next, as shown in FIG. 10, the insulating film IF5, the silicon filmPS3, the metal film TN, and the insulating films HK and IF4 in theperipheral circuit region 1B, and besides, the insulating film IF2, thesilicon film PS1 and the insulating film IF1 in the peripheral circuitregion 1C are patterned by using a photolithography technique and anetching technique. Thus, in the peripheral circuit region 1B, the dummygate electrode DG made of the silicon film PS3, the metal film TN and agate insulating film GIL made of the insulating films HK and IF4, whichconfigure the MISFET (Q1), are formed. Simultaneously, in the peripheralcircuit region IC, a gate electrode G2 and a gate insulating film GIH,which configure the MISFET (Q2), are formed.

Here, in a state in which the memory cell region 1A is covered with aresist film, first, the insulating film IF5 in the peripheral circuitregion 1B and the insulating film IF2 in the peripheral circuit region1C are patterned by a photolithography technique and an etching method.Then, in the peripheral circuit region 1B, the silicon film PS3, themetal film TN, and the insulating films HK, IF4 and IF1 are patterned bythe etching process while using the patterned insulating film IF5 as ahard mask, so that the gate insulating film GIL configured by the dummygate electrode DG, the metal film TN and the insulating films HK and IF4is formed. Moreover, in the peripheral circuit region 1C, the siliconfilm PS1 and the insulating film IF4 are patterned by the etchingprocess while using the patterned insulating film IF2 as a hard mask, sothat the gate electrode G2 and the gate insulating film GIH are formed.

Next, as shown in FIG. 11, a plurality of extension regions (n⁻-typesemiconductor regions, impurity diffusion regions) EX are formed byusing an ion implantation method or others. That is, in the activeregion, while an n-type impurity such as arsenic (As) or phosphorus (P)is introduced into the surface of the semiconductor substrate SB, noimpurity is introduced into the lower portions of the control gateelectrode CG, the memory gate electrode MG, the dummy gate electrode DGand the gate electrode G2. That is, in the active region, the extensionregions EX are formed on both sides of the control gate electrode CG andmemory gate electrode MG, both sides of the dummy gate electrode DG andboth sides of the gate electrode G2. Prior to the formation of theextension regions EX, an offset spacer that covers each of the sidewallsof the control gate electrode CG, the memory gate electrode MG, thedummy gate electrode DG and the gate electrode G2 may be formed of, forexample, a silicon nitride film, a silicon oxide film or a stacked filmof these films.

The extension region EX of each of the memory cell region 1A and theperipheral circuit regions 1B and 1C can be formed by the same ionimplantation method as each other. However, they can be also formed byusing a different ion implantation process. Although its illustration isomitted, note that, before or after the formation process of theextension regions EX, for example, a halo region may be formed on themain surface of the semiconductor substrate SB in the peripheral circuitregion 1B by implanting a p-type impurity (for example, boron (B)) whileusing the insulating film IF5 and the dummy gate electrode DG as a mask.The halo region is closer to the center of the dummy gate electrode DGthan the extension regions EX. That is, the halo region is formed at aportion close to the channel region of the low breakdown voltage MISFET(Q1) formed in the peripheral circuit region 1B. By forming the haloregion, the short channel characteristics of this MISFET can beimproved. Similarly, the halo region may be formed at a portion close tothe channel region of the high breakdown voltage MISFET (Q2).

Subsequently, sidewalls SW made of an insulating film covering thesidewalls on both sides of the above-described structure including thecontrol gate electrode CG and the memory gate electrode MG in the memorycell region 1A are formed. Moreover, by this process, sidewalls SWcovering the sidewalls on both sides of the stacked body configured bythe gate insulating film GIL, the metal film TN, the dummy gateelectrode DG and the insulating film IF5 are formed in the peripheralcircuit region 1B. Furthermore, by this process, sidewalls SW coveringthe sidewalls on both sides of the stacked body configured by the gateinsulating film GIH, the gate electrode G2 and the insulating film IF2are formed in the peripheral circuit region 1C.

In the sidewalls SW, after sequentially forming, for example, a siliconoxide film and a silicon nitride film on the semiconductor substrate SBby using a CVD method or others, a part of the silicon oxide film andthe silicon nitride film is removed by an anisotropic etching process sothat the upper surface of the semiconductor substrate SB and the uppersurfaces of the insulating films IF2 and IF5 are exposed. Thus, thesidewalls SW can be selectively formed on the sidewalls of the controlgate electrode CG, the memory gate electrode MG, the dummy gateelectrode DG and the gate electrode G2. While it is considered that thesidewalls SW are formed of a stacked film, the drawings do not show aninterface between the films configuring the stacked film. The sidewallsSW may be formed of, for example, a single layer film such as a siliconoxide film or a silicon nitride film.

Subsequently, diffusion regions (n⁺-type semiconductor regions, impuritydiffusion regions) DF are formed in the memory cell region 1A and theperipheral circuit regions 1B and 1C by using an ion implantation methodor others. That is, while an n-type impurity such as arsenic (As) orphosphorus (P) is introduced into the surface of the semiconductorsubstrate SB in the active region, no impurity is introduced into thelower portions of the control gate electrode CG, the memory gateelectrode MG, the dummy gate electrode DG, the gate electrode G2 and thesidewalls SW. That is, in the active region, the diffusion regions DFare formed on both sides of the control gate electrode CG and memorygate electrode MG, both sides of the dummy gate electrode DG and bothsides of the gate electrode G2, and besides, formed outside eachsidewall SW. The diffusion region DF has a higher impurity concentrationand a larger junction depth than those of the extension region EX.

Thus, the source region and the drain region having an LDD structureconfigured by the extension region EX and a diffusion region DF havingan impurity concentration higher than that of the extension region EXare formed.

In the memory cell region 1A, the extension region EX and the diffusionregion DF formed on the upper surface of the semiconductor substrate SBso as to sandwich the control gate electrode CG and the memory gateelectrode MG configure the source region and the drain region of thememory cell MC. Moreover, in the peripheral circuit region 1B, theextension region EX and the diffusion region DF formed on the uppersurface of the semiconductor substrate SB so as to sandwich the dummygate electrode DG configure the source region and the drain region ofthe low breakdown voltage MISFET (Q1). In the peripheral circuit region1C, the extension region EX and the diffusion region DF formed on theupper surface of the semiconductor substrate SB so as to sandwich thegate electrode G2 configure the source region and the drain region ofthe high breakdown voltage MISFET (Q2). The diffusion region DF formedin each of the memory cell region 1A and the peripheral circuit regions1B and 1C can be formed by the same ion implantation process as eachother. However, these diffusion regions DF can be also formed by usingdifferent ion implantation processes from each other.

Subsequently, an activation annealing process, which is a thermaltreatment for activating the impurity introduced into the semiconductorregion (extension region EX and diffusion region DF) for the source anddrain or others, is performed.

Next, a silicide layer is formed by performing a so-called salicide(Salicide: Self-Aligned Silicide) process which is explained withreference to FIGS. 12 and 13. More specifically, the silicide layer canbe formed as follows.

That is, as shown in FIG. 12, by performing a chemical dry etchingprocess onto the main surface of the semiconductor substrate SB as apretreatment, an excessive silicon oxide film or others on thesemiconductor substrate SB is removed so as to expose the surface of thesemiconductor. Subsequently, a metal film MF1 for use in forming asilicide layer is formed (deposited) on the main surface of thesemiconductor substrate SB including the upper surface of the diffusionregion DF and the upper surface of the memory gate electrode MG. Thefilm thickness of the metal film MF1 is set to, for example, 20 to 25nm.

The metal film MF1 can be formed by a sputtering method using, forexample, an alloy target formed by adding platinum (Pt) to nickel (Ni).The content (concentration) of platinum (Pt) that is an additive to thealloy target is set to 5% or more (more preferably, 5% or more and 10%or less). The additive may be aluminum (Al), carbon (C) or others. Thecontent (concentration) in this case is also set to 5% or more (morepreferably, 5% or more and 10% or less). However, platinum has higherheat resistance than that of aluminum, carbon or others, and therefore,can be preferably used for the alloy film. The metal film MF1 formed bythe sputtering method using the alloy target is a nickel (Ni) filmcontaining platinum (Pt), and the content of platinum (Pt) is 5% ormore. Here, nickel serving as a main material is referred to as firstmetal, and platinum (Pt) serving as an additive is referred to as secondmetal.

Next, by performing a first thermal treatment onto the semiconductorsubstrate SB, the respective surface layer portions of the diffusionregion DF and the memory gate electrode MG are allowed to react with themetal film MF1. This first thermal treatment is a thermal treatment forallowing the metal film MF1 to react with silicon of the diffusionregion DF and the memory gate electrode. By the first thermal treatment,a silicide layer in which NiSi fine crystals and Ni₂Si are dominant isformed on the respective upper portions of the diffusion region DF andthe memory gate electrode MG. At this stage, the silicide layer is asilicide layer having comparatively high resistance which is differentfrom the silicide layer S1 shown in FIG. 1. Moreover, since the platinum(Pt) serving as the additive has a small content, no platinum silicideis formed, so that the crystals of the silicide layer and the silicidelayer S1 to be explained later are described as NiSi and Ni₂Si so as notto contain Pt. Next, after the first thermal treatment, the unreactedportion of the metal film MF1 with silicon is removed by wet etching orothers, and then, second thermal treatment is performed onto thesemiconductor substrate SB. The second thermal treatment is executed inorder to promote the crystal growth of the silicide layer havingcomparatively high resistance to form the silicide layer S1 havingcomparatively low resistance in which NiSi is dominant. The temperatureof the second thermal treatment is higher than the temperature of thefirst thermal treatment. Thus, the silicide layer S1 made of NiSi isformed.

For the above-described two thermal treatments, for example, a thermaltreatment apparatus for heating the semiconductor substrate SB by usinga carbon heater is used. In the first thermal treatment, the silicidelayer having comparatively high resistance is formed by, for example,the heating at a temperature of about 260° C. for 30 to 60 seconds.Then, after the unreacted part of the metal film MF1 is removed by wetetching or others as described above, the second thermal treatment isfurther performed at 600° C. for 10 to 30 seconds, so that the silicidelayer S1 having the reduced resistance is grown. Here, by separatelyperforming the thermal treatments as described above, such abnormalgrowth of the silicide layer S1 as extending inside the semiconductorsubstrate SB can be prevented. Moreover, in the formation of thesilicide layer S1, the abnormal growth of the silicide layer S1 can besuppressed by using nickel (Ni) metal containing platinum (Pt), so thata leak current in the diffusion region DF (in other words, the sourceregion or the drain region) can be reduced.

Here, the second thermal treatment is performed at, for example, atemperature of 450° C. or higher and 600° C. or lower. In the presentembodiment, as described above, the second thermal treatment isperformed at 600° C. Note that the second thermal treatment may beperformed by using a laser, microwaves or a flash lamp.

In this manner, since the second thermal treatment is performed at avery high temperature, the silicide layer S1 formed by the thermaltreatment has a comparatively high tensile stress. By application ofthis tensile stress to the memory cell MC and channels of the lowbreakdown voltage MISFET (Q1) and the high breakdown voltage MISFET(Q2), the mobility of electrons or positive holes is improved, so thatthe memory cell MC, the low breakdown voltage MISFET (Q1) and the highbreakdown voltage MISFET (Q2) can be operated at a high speed.

Note that the upper surfaces of the control gate electrode CG and thegate electrode G2 are covered with the insulating film IF2, and theupper surface of the dummy gate electrode DG is covered with theinsulating film IF5, and therefore, no silicide layer S1 is formed onthe upper portions of the control gate CG, the gate electrode G2 and thedummy gate electrode DG. Since the upper portion of the sidewall-shapedmemory gate electrode MG is exposed, the silicide layer S1 is formed onthe exposed portion. However, this silicide layer S1 is completelyremoved by a polishing process based on a CMP (Chemical MechanicalPolishing) method to be performed in a later process.

Next, as shown in FIG. 14, on the main surface of the semiconductorsubstrate SB, an insulating film (liner insulating film) IF7 and aninterlayer insulating film IL1 are subsequently formed so as to coverthe control gate electrode CG, the memory gate electrode MG, the dummygate electrode DG, the gate electrode G2 and the sidewalls SW. Theinsulating film IF7 is made of, for example, a silicon nitride film, andcan be formed by, for example, a CVD method. The insulating film IF7 canbe used as an etching stopper film when a contact hole is formed in alater process. The interlayer insulating film IL1 is made of, forexample, a single film of a silicon oxide film, and can be formed by,for example, a CVD method or others. Here, the interlayer insulatingfilm IL1 is formed with, for example, a film thickness larger than thefilm thickness of the control gate electrode CG.

Next, as shown in FIG. 15, the upper surface of the interlayerinsulating film IL1 is polished by using a CMP method or others. In thismanner, the upper surface of each of the control gate electrode CG, thememory gate electrode MG, the dummy gate electrode DG, and the gateelectrode G2 is exposed. That is, in this polishing process, theinterlayer insulating film IL1 and the insulating film IF7 are polisheduntil the upper surface of each of the control gate electrode CG, thememory gate electrode MG, the dummy gate electrode DG, and the gateelectrode G2 is exposed. In this manner, the insulating films IF2 andIF5 are removed, and the upper portion of each of the sidewall SW andthe gate insulating film GIm is partially removed. In addition, by thisprocess, the silicide layer 51 on the memory gate electrode MG isremoved together with a part of the upper portion of the memory gateelectrode MG. At this stage, since the gate insulating film GIm and thesidewalls SW or others, located between the control gate electrode CGand the memory gate electrode MG, are polished all together, the heightsof the gate insulating film GIm and the sidewalls SW are almost equal tothe height of the control gate electrode CG or the memory gate electrodeMG.

Next, as shown in FIG. 16, after the insulating film IF8 is formed onthe interlayer insulating film IL1 by using, for example, a CVD method,the insulating film IF8 is processed by using a photolithographytechnique and an etching method. In this manner, the insulating film IF8covers the memory cell region 1A and the peripheral circuit region 1C,and exposes the dummy gate electrode DG in the peripheral circuit region1B. That is, the insulating film IF8 covers the upper surfaces of thecontrol gate electrode CG, the memory gate electrode MG, and the gateelectrode G2, and exposes the upper surface of the dummy gate electrodeDG. The insulating film IF8 is made of, for example, a silicon oxidefilm.

Then, the dummy gate electrode DG is removed by a wet etching method.Here, the dummy gate electrode DG is removed by the wet etching processusing, for example, alkaline aqueous solution while using the insulatingfilm IF8 as a mask for protecting the control gate electrode CG, thememory gate electrode MG and the gate electrode G2. As the alkalineaqueous solution, for example, ammonia hydrogen peroxide mixture(NH₄OH+H₂O₂+H₂O) is used. By removing the dummy gate electrode DG, atrench (concave portion, hollow portion) is formed in the metal film TN.The trench on the metal film TN in the peripheral circuit region 1B is aregion from which the dummy gate electrode DG is removed, and thesidewalls on both sides of the trench are formed of the sidewalls SW.

Next, as shown in FIG. 16, that is, a metal film is formed as aconductive film for the gate electrode on the semiconductor substrateSB, that is, on the interlayer insulating film IL1 including the upperportion of the inner surface (bottom surface and sidewalls) of theabove-described trench so as to completely bury the trench. Note thatthe metal film is considered to have, for example, a stacked structureof two or more metal films. However, in the drawing, the illustration ofthe border between the two or more metal films is omitted, and the metalfilm is shown as a single film.

In the formation process of the metal film, the inside of the trench iscompletely filled. In addition, the metal film is also formed on theinterlayer insulating film IL1. As the metal film, for example, atitanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungstennitride (WN) film, a titanium carbide (TiC) film, a tantalum carbide(TaC) film, a tungsten carbide (WC) film, a tantalum carbide nitride(TaCN) film, a titanium (Ti) film, a tantalum (Ta) film, a titaniumaluminum (TiAl) film, an aluminum (Al) film, or others can be used. Notethat the term “metal film” described here means a conductive filmexhibiting metallic conduction, and includes not only a single metalfilm (pure metal film) or an alloy film, but also a metallic compoundfilm exhibiting the metallic conduction. The metal film can be formed byusing, for example, a sputtering method or others.

Here, for example, the metal film can be formed of, for example, astacked film of a titanium nitride (TiN) film and an aluminum (Al) filmon the titanium nitride film. At this stage, it is preferable to makethe aluminum film thicker than the titanium nitride film. Since thealuminum film has low resistance, the resistance of the gate electrodeG1 to be formed later can be reduced.

Then, by polishing and removing the unnecessary portions of the metalfilm outside the trenches by a CMP method or others, the metal film isburied into the trenches. Thus, the gate electrode G1 of the lowbreakdown voltage MISFET (Q1) in the peripheral circuit region 1B isformed. As described above, the entire gate electrode G1 is made of ametal film, and therefore, there is no problem for, for example, adepleted gate electrode as observed in the case of the usage of thepolysilicon film. Although its illustration is omitted, note that thegate electrode of the p-type low breakdown voltage MISFET in theperipheral circuit region 1B can be formed by burying a metal filmdifferent from that of the gate electrode G1 of the low breakdownvoltage MISFET (Q1), by repeating the same processes as described above.

Next, by removing the insulating film IF8 by using, for example, a wetetching method or others, the control gate electrode CG, the memory gateelectrode MG and the gate electrode are exposed as shown in FIG. 17.

Next, as explained with reference to FIGS. 18 and 19, a silicide layeris formed on each of the electrodes made of a polysilicon film byperforming the salicide process. More specifically, the silicide layercan be formed as follows.

That is, as shown in FIG. 18, the pattern of an insulating film IF9 thatcovers the peripheral circuit region 1B is formed by using, for example,a CVD method, a photolithography technique and an etching technique. Theinsulating film IF9 is an insulating film which exposes the uppersurfaces of the control gate electrode CG and the memory gate electrodeMG in the memory cell region 1A and the gate electrode G2 in theperipheral circuit region 1C and which covers the gate electrode G1 inthe peripheral circuit region 1B, and is made of, for example, a siliconoxide film or others.

Subsequently, by performing a chemical dry etching process onto the mainsurface of the semiconductor substrate SB as a pretreatment, eachexcessive silicon oxide film or others on the control gate electrode CG,on the memory gate electrode MG, and on the gate electrode G2 is removedso as to expose each surface of the control gate electrode CG, thememory gate electrode MG, and the gate electrode G2. Subsequently, ametal film MF2 for use in forming a silicide layer is formed (deposited)on the main surface of the semiconductor substrate SB including theupper surface of the memory gate electrode MG and the upper surface ofthe gate electrode G2. The film thickness of the metal film MF2 is setto, for example, 20 to 25 nm.

The metal film MF2 can be formed by a sputtering method using, forexample, an alloy target formed by adding platinum (Pt) to nickel (Ni).The content (concentration) of platinum (Pt) that is an additive to thealloy target is set to less than 5%. The additive may be aluminum (Al),carbon (C) or others. The content (concentration) in this case is alsoset to less than 5%. However, platinum has higher heat resistance thanthat of aluminum, carbon or others, and therefore, can be preferablyused for the alloy film. The metal film MF2 formed by the sputteringmethod using the alloy target is a nickel (Ni) film containing platinum(Pt), and the content of platinum (Pt) is less than 5%. Also here,nickel serving as a main material is referred to as first metal, andplatinum (Pt) serving as an additive is referred to as second metal.

Next, by performing a third thermal treatment (referred to as thirdthermal treatment in order to be distinguished from the above-describedfirst and second thermal treatments) onto the semiconductor substrateSB, the respective surface layer portions of the control gate electrodeCG, the memory gate electrode MG, and the gate electrode G2 are allowedto react with the metal film MF2. This third thermal treatment is athermal treatment for allowing the metal film MF2 to react with siliconof the control gate electrode CG, the memory gate electrode MG, and thegate electrode G2. By the third thermal treatment, a silicide layer inwhich NiSi fine crystals and Ni₂Si are dominant is formed on therespective upper portions of the control gate electrode CG, the memorygate electrode MG, and the gate electrode G2. At this stage, thesilicide layer is a silicide layer having comparatively high resistancewhich is different from the silicide layer S2 shown in FIG. 1. Moreover,since the platinum (Pt) serving as the additive has a small content asdescribed above, no platinum silicide is formed, so that the crystals ofthe silicide layer comparatively high resistance and the silicide layerS2 to be explained later are described as NiSi and Ni₂Si so as not tocontain Pt. Next, after the third thermal treatment, the unreactedportion of the metal film MF2 with silicon is removed by wet etching orothers, and then, fourth thermal treatment is performed onto thesemiconductor substrate SB. The fourth thermal treatment is executed inorder to promote the crystal growth of the silicide layer havingcomparatively high resistance to form the silicide layer S2 havingsufficiently reduced resistance in which NiSi is dominant. Thetemperature of the fourth thermal treatment is higher than thetemperature of the third thermal treatment. Thus, the silicide layer S2made of NiSi is formed.

In this manner, as shown in FIG. 19, the silicide layer S2 isselectively formed on the upper surfaces of the control gate electrodeCG, the memory gate electrode MG and the gate electrode G2.

For the above-described third and fourth thermal treatments, forexample, a thermal treatment apparatus for heating the semiconductorsubstrate by using a carbon heater is used. That is, in the fourththermal treatment, the silicide layer S2 containing NiSi fine crystalsand Ni₂Si is formed by, for example, the heating at a temperature ofabout 260° C. for 10 to 30 seconds. Then, after the unreacted part ofthe metal film MF2 is removed by wet etching or others as describedabove, the fourth thermal treatment is further performed at 400° C. for30 to 60 seconds, so that the NiSi crystals inside the silicide layer S2is grown.

The silicide layer S2 formed in this manner is made of, for example,nickel silicide (NiSi) containing platinum. However, the layer is notalways required to contain platinum (Pt). In the case containingplatinum (Pt), the third thermal treatment can be executed at a lowertemperature, so that the short circuit between the silicide layers S2formed on the surfaces (upper surfaces) of the control gate electrode CGand the memory gate electrode MG can be prevented. In the split-gatetype memory cell MC of the present embodiment, the upper surface of thecontrol gate electrode CG, the upper surface of the memory gateelectrode MG and the ends of the gate insulating film GIm have almostthe same height as one another, and the silicide layer S2 is formed onthe upper surface of the control gate electrode CG and the upper surfaceof the memory gate electrode MG. In other words, the silicide layer S2on the upper surface of the control gate electrode CG and the silicidelayer S2 on the upper surface of the memory gate electrode MG areconfigured to easily cause the short circuit therebetween. However,since platinum (Pt) is contained in the silicide layer S2, thisconfiguration has such effect as preventing the above-described shortcircuit. If the silicide layer is formed by using a nickel (Ni) film notcontaining platinum (Pt), the temperature of the above-described thirdthermal treatment needs to be set to about 400° C. However, when thethird thermal treatment is performed at such a high temperature, aproblem of the short circuit between the control gate electrode CG andthe memory gate electrode MG through the silicide layer is caused.

Here, the above-described fourth thermal treatment is performed at, forexample, a temperature of 400° C. or less. In the present embodiment, asdescribed above, it is important to execute the fourth thermal treatmentat a temperature lower than that of the second thermal treatment. Inthis case, it is important to execute the fourth thermal treatment for aperiod of time longer than that of the second thermal treatment, andthis long execution can achieve the sufficiently reduced resistance ofthe silicide layer S2. In this manner, by performing the fourth thermaltreatment at a temperature lower than that of the second thermaltreatment, each of the silicide layers S2 formed on the surfaces (uppersurfaces) of the control gate electrode CG, the memory gate electrode MGand the gate electrode G2 can be formed as, for example, a film havingtensile stress lower than that of the silicide layer S1 formed on thesurface of the diffusion region DF, and therefore, the silicide layer S2has such features as being difficult to disconnect and as having a smallsheet resistance.

Next, as shown in FIG. 20, an interlayer insulating film and a pluralityof contact plugs are formed. Here, first, an interlayer insulating filmIL2 that covers the upper surface of the semiconductor substrate SBincluding the memory cell region 1A and the peripheral circuit regions1B and 1C is formed by using, for example, a CVD method. The interlayerinsulating film IL2 is made of, for example, a silicon oxide film, andcovers the respective upper surfaces of the control gate electrode CG,the memory gate electrode MG, the gate electrodes G1 and G2, and theinterlayer insulating film IL1. In the peripheral circuit region 1B, theinsulating film IF9 formed at the time of the formation of the silicidelayer S2 is left. If needed, the insulating film IF9 may be removedbefore the formation of the interlayer insulating film IL2.

Subsequently, by using a photolithography technique, the interlayerinsulating films IL2 and IL1 and the insulating films IF9 and IF7 aredry-etched while using the resist film (not shown) formed on theinterlayer insulating film IL2 as an etching mask. Thus, a plurality ofcontact holes (openings, through holes) that penetrate the interlayerinsulating film IL2 and a plurality of contact holes that penetrate theinterlayer insulating films IL1 and IL2 and the insulating film IF7 areformed. Note that the contact holes in the peripheral circuit region 1Bpenetrate the insulating film IF9.

From the bottoms of the respective contact holes, a part of the mainsurface of the semiconductor substrate SB such as a part of the silicidelayer S1 on the surface of the diffusion region DF, a part of thesilicide layer S2 on the surface of the control gate electrode CG, apart of the silicide layer S2 on the surface of the memory gateelectrode MG or a part of the gate electrodes G1 and G2 are exposed.Note that the contact holes on the respective gate electrodes are formedin regions not shown in FIG. 20.

Subsequently, inside the respective contact holes, conductive contactplugs CP made of tungsten (W) or others are formed as conductors forconnection. In order to form the contact plugs CP, for example, abarrier conductor film (for example, titanium film, titanium nitridefilm or stacked film of them) is formed on the interlayer insulatingfilm IL2 including the insides of the contact holes. Then, a mainconductor film made of a tungsten film or others is formed on thisbarrier conductor film so as to completely fill the inside of therespective contact holes, and then, the unnecessary main conductor filmand barrier conductor film outside each contact hole are removed byusing a CMP method, an etching back method or others, so that thecontact plugs CP can be formed. In order to simplify the drawing, notethat FIG. 20 shows the barrier conductor film and the main conductorfilm (tungsten film) configuring the contact plug CP so as to beintegrated.

The contact plug CP filled inside the contact hole is formed so as to berespectively connected to each upper portion of the diffusion region DF,the control gate electrode CG, the memory gate electrode MG, and thegate electrode G1 or the gate electrode G2. In other words, the contactplug CP is connected to the upper surface of each of the diffusionregions DF of the memory cell MC, the low breakdown voltage MISFET (Q1)and the high breakdown voltage MISFET (Q2), via the silicide layer S1.Moreover, the contact plug CP is connected to the upper surface of eachof the control gate electrode CG, the memory gate electrode MG and thegate electrode G2, via the silicide layer S2.

Then, as shown in FIG. 1, on the interlayer insulating film IL2 intowhich the contact plug CP is buried, a first wiring layer M1 including afirst-layer wiring is formed. A plurality of first-layer wirings areconnected to the respective upper surfaces of the contact plugs CP shownin FIG. 1. Then, a second wiring layer, a third wiring layer or othersare subsequently formed on the first wiring layer to form a stackedwiring layer, and then, the semiconductor wafer is divided intoindividual pieces by a dicing process, so that a plurality ofsemiconductor chips are obtained. As described above, the semiconductordevice of the present embodiment is manufactured.

<Characteristics and Effects of Method for Manufacturing SemiconductorDevice of Present Embodiment>

For example, in a method for manufacturing a semiconductor device havingthe MISFET (Q2), diffusion regions DF configuring a source region and adrain region are formed so as to sandwich a gate electrode G2therebetween, and next, a silicide layer S1 is formed on the surfaces ofthe diffusion regions DF while the gate electrode G2 is covered with aninsulating film IF2. Then, the insulating film IF2 on the gate electrodeG2 is removed, and a silicide layer S2 is formed on the surface (uppersurface) of the exposed gate electrode G2. The silicide layers S1 and S2are formed of a first metal (for example, nickel) and silicon, andcontain a second metal (for example, platinum) as an additive.

According to the above-described manufacturing method, since thesilicide layer S1 and the silicide layer S2 are formed by differentprocesses from each other, the additive concentration of the silicidelayer S2 can be made lower than the additive concentration of thesilicide layer S1. That is, a leak current in the source region or thedrain region of the MISFET (Q2) can be reduced, and the sheet resistanceof the silicide layer S2 on the gate electrode G2 can also be reduced.

In the formation of the above-described silicide layers S1 and S2, bysetting the fourth thermal treatment temperature for forming thesilicide layer S2 to a temperature lower than the second thermaltreatment temperature for forming the silicide layer S1, the tensilestress exerted inside the silicide layer S2 can be reduced, so that theprevention of the disconnection of the gate electrode G2 and thereduction of the resistance can be achieved.

Moreover, the above-described semiconductor device further has theMISFET (Q1) having the metal gate electrode G1. In the MISFET (Q2),diffusion regions DF forming the source region and the drain region areformed on both ends of the dummy electrode DG, and next, the silicidelayer S1 is formed on the surface of the diffusion regions D while thedummy gate electrode DG is covered with the insulating film IF5.Moreover, after the insulating film IF5 on the dummy gate electrode DGis removed, the dummy gate electrode DG is removed, and the metal gateelectrode G1 is formed. The process for forming the silicide layer S1 ofthe MISFET (Q2) is performed by the same process as the process forforming the silicide layer S1 of the MISFET (Q1). Furthermore, theprocess for removing the insulating film IF2 on the gate electrode G2 ofthe MISFET (Q2) is performed by the same process as the process forremoving the insulating film IF5 on the dummy gate electrode DG. Thatis, by utilizing (sharing) the process for forming the MISFET (Q1)having the metal gate electrode G1, the silicide layers S1 and S2 of theMISFET (Q2) are formed by different processes.

For example, in a method for manufacturing a semiconductor device havinga nonvolatile memory cell MC, the diffusion regions DF for forming thesource region and the drain region are formed so as to sandwich thecontrol gate electrode CG and the memory gate MG, and next, a silicidelayer S1 is formed on the surfaces of the memory gate electrode MG andthe diffusion layers DF while the control gate electrode CG is coveredwith the insulating film IF2. Then, by removing the insulating film IF2on the control gate electrode CG and the silicide layer S1 on the memorygate electrode MG, a silicide layer S2 is formed on the surfaces (uppersurfaces) of the exposed control gate electrode CG and memory gateelectrode MG. The silicide layers S1 and S2 are formed of a first metal(for example, nickel) and silicon, and contain a second metal (forexample, platinum) as an additive.

According to the above-described manufacturing method, since thesilicide layer S1 and the silicide layer S2 are formed by differentprocesses from each other, the additive concentration of the silicidelayer S2 can be made lower than the additive concentration of thesilicide layer S1. That is, a leak current in the source region or thedrain region of the nonvolatile memory cell can be reduced, the sheetresistance of the silicide layer S2 on each of the control gateelectrode CG and on the memory gate electrode MG can also be reduced,and the high-speed operation of the semiconductor device having thenonvolatile memory cell MC can be achieved.

In the formation of the above-described silicide layers S1 and S2, bysetting the fourth thermal treatment temperature for forming thesilicide layer S2 to a temperature lower than the second thermaltreatment temperature for forming the silicide layer S1, the tensilestress exerted inside the silicide layer S2 can be reduced, so that theprevention of the disconnection of the control gate electrode CG and thememory gate electrode MG and the reduction of the resistance can beachieved.

Moreover, in the formation of the above-described silicide layer S2, bythe usage of the nickel film containing platinum, the third thermaltreatment temperature can be lower than that in the usage of the nickelfilm not containing platinum, the short circuit between the silicidelayer S2 on the control gate electrode CG and the silicide layer S2 onthe memory gate electrode MG can be prevented.

Next, modified examples of the present embodiment will be described.

FIRST MODIFIED EXAMPLE

As explained with reference to FIG. 13, in the above-describedembodiment, after the metal film MF1 is formed by a sputtering methodusing an alloy target formed by adding platinum (Pt) to nickel (Ni), thesilicide layer S1 is formed by performing the above-described first andsecond thermal treatments on the semiconductor substrate SB.

In a first modified example, after a metal film MF3 is formed by asputtering method or a CVD method using a nickel (Ni) target notcontaining platinum (Pt), platinum (Pt) is introduced into the metalfilm MF3 by using an ion implantation method. Then, by performing theabove-described first and second thermal treatments on the metal filmMF3 to which platinum (Pt) has been introduced, the silicide layer S1can be formed. Of course, the content (concentration) of platinum (Pt)contained in the silicide layer S1 is set to 5% or more (morepreferably, 5% or more and 10% or less).

Moreover, in the formation of the silicide layer S2, as similar to theabove description, after a metal film MF4 is formed by a sputteringmethod or a CVD method using a nickel (Ni) target not containingplatinum (Pt), platinum (Pt) may be introduced into the metal film MF4by using an ion implantation method. Then, by performing theabove-described third and fourth thermal treatments on the metal filmMF4 to which platinum (Pt) has been introduced, the silicide layer S2can be formed. Of course, the content (concentration) of platinum (Pt)contained in the silicide layer S2 is set to less than 5%.

Note that both of the silicide layer S1 and the silicide layer S2 maynot be formed by using the method of the first modified example. Forexample, one of them may be formed by using the method of the firstmodified example, and the other may be formed by using the method of thefirst embodiment.

SECOND MODIFIED EXAMPLE

A second modified example relative to the first modified example will bedescribed.

In the first modified example, after platinum (Pt) is introduced to themetal film MF3 by using an ion implantation method, the above-describedfirst and second thermal treatments are performed, so that the silicidelayer S1 is formed. However, in the second modified example, after thefirst and second thermal treatments, platinum (Pt) is introduced intothe silicide layer S1 by using the ion implantation method. That is, asilicide layer (referred to as “sub-silicide layer”) not containingplatinum (Pt) is formed by the above-described first and second thermaltreatments, and platinum (Pt) is ion implanted into the sub-silicidelayer, so that a silicide layer S1 containing platinum (Pt) is formed.Of course, the content (concentration) of platinum (Pt) contained in thesilicide layer S1 is set to 5% or more (more preferably, 5% or more and10% or less).

Moreover, also in the formation of the silicide layer S2, as similar tothe above description, after the third and fourth thermal treatments,platinum (Pt) is introduced into the silicide layer S2 by using the ionimplantation method. That is, a sub-silicide layer not containingplatinum (Pt) is formed by the above-described third and fourth thermaltreatments, and platinum (Pt) is ion implanted into the sub-silicidelayer, so that a silicide layer S2 containing platinum (Pt) is formed.Of course, the content (concentration) of platinum (Pt) contained in thesilicide layer S2 is set to less than 5%.

According to the second modified example, the abnormal growth of thesilicide layer relative to a thermal load after the formation of thesilicide layer S1 can be suppressed, and so that the leak current in thesource region and the drain region can be reduced.

Note that both of the silicide layer S1 and the silicide layer S2 maynot be formed by using the method of the second modified example. Forexample, one of them may be formed by using the method of the secondmodified example, and the other may be formed by using the method of thefirst embodiment or the first modified example.

In the above-described embodiment and modified embodiments, theexplanations have been made while exemplifying a memory cell having asplit-gate type MONOS structure having a control gate electrode and amemory gate electrode sandwiched by a source region and a drain regionas a nonvolatile memory cell. However, a memory cell having asingle-gate type MONOS structure may be also applicable. The memory cellin this case has: a source region and a drain region formed inside asemiconductor substrate; a gate electrode; and a stacked film which isformed between the semiconductor substrate and the gate electrode andwhich includes a silicon oxide film OX1, a silicon nitride film NTformed on the silicon oxide film OX1 and a silicon oxide film OX2 formedon the silicon nitride film NT. Moreover, the above-described silicidelayer S1 is formed on the surfaces of the source region and the drainregion, and the silicide layer S2 is formed on the gate electrode, andthe content (concentration) of an additive (for example, platinum)contained in the silicide layer S2 is set to be lower than the content(concentration) of an additive (for example, platinum) contained in thesilicide layer S1.

In the foregoing, the invention made by the present inventor has beenconcretely described based on the embodiments. However, it is needlessto say that the present invention is not limited to the foregoingembodiments and various modifications and alterations can be made withinthe scope of the present invention.

For example, in the present embodiment, nickel (Ni) is exemplified asthe first metal. However, in place of this, titanium (Ti) or cobalt canbe also used. Moreover, platinum (Pt) is exemplified as the secondmetal. However, in place of this, tantalum (Ta), palladium (Pd),aluminum (Al), manganese (Mn) or tungsten (W) can be also used.

In addition, a part of the contents described in the above-describedembodiment will be described below.

[Additional Note 1]

In a semiconductor device having a first MISFET in a first region of asemiconductor substrate, the first MISFET includes: a first gateinsulating film formed on the semiconductor substrate in the firstregion; a first gate electrode formed on the first gate insulating film;first impurity regions which are formed inside the semiconductorsubstrate so as to sandwich the first gate electrode in the first regionand which configure a part of a first source region and a part of afirst drain region; a first silicide layer which is formed on the firstimpurity region and which contains a first metal and silicon; and asecond silicide layer which is formed in an upper portion of the firstgate electrode and which contains the first metal and silicon. A secondmetal different from the first metal is added into the first silicidelayer, and a concentration of the second metal inside the secondsilicide layer is lower than a concentration of the second metal insidethe first silicide layer.

EXPLANATION OF REFERENCE CHARACTERS

1A memory cell region

1B, 1C peripheral circuit region

CG control gate electrode

CP contact plug

DF diffusion region

DG dummy gate electrode

EX extension region

G1, G2 gate electrode

GIm, GIt, GIH, GIL gate insulating film

HK insulating film

IF1 to IF9 insulating film

IL1, IL2 interlayer insulating film

M1 wiring layer

MC memory cell

MF1, MF2, MF3, MF4 metal film

MG memory gate electrode

ON insulating film

PS1, PS2, PS3 silicon layer

PW1, PW2, PW3 p-type well

Q1, Q2 MISFET

SB semiconductor substrate

S1, S2 silicide layer

ST element isolation region

SW sidewall

TN metal film

1. A semiconductor device comprising a first MISFET in a first region ofa semiconductor substrate, wherein the first MISFET includes: a firstgate insulating film formed on the semiconductor substrate in the firstregion; a first gate electrode formed on the first gate insulating film;first impurity regions which are formed inside the semiconductorsubstrate so as to sandwich the first gate electrode in the first regionand which configure a part of a first source region and a part of afirst drain region; a first silicide layer which is formed on the firstimpurity region and which contains a first metal and silicon; and asecond silicide layer which is formed in an upper portion of the firstgate electrode and which contains the first metal and silicon, a secondmetal different from the first metal is added to the first silicidelayer and the second silicide layer, and a concentration of the secondmetal inside the second silicide layer is lower than a concentration ofthe second metal inside the first silicide layer.
 2. The semiconductordevice according to claim 1, further comprising: a second MISFET in asecond region different from the first region of the semiconductorsubstrate, wherein the second MISFET includes: a second gate insulatingfilm formed on the semiconductor substrate in the second region; asecond gate electrode which is formed on the second insulating film andwhich is made of a metal film; second impurity regions which are formedinside the semiconductor substrate so as to sandwich the second gateelectrode in the second region and which configure a part of a secondsource region and a part of a second drain region; and a third silicidelayer which is formed on the second impurity region and which containsthe first metal and silicon, the second metal is added into the thirdsilicide layer, and a concentration of the second metal inside thesecond silicide layer is lower than a concentration of the second metalinside the third silicide layer.
 3. The semiconductor device accordingto claim 2, wherein the second gate insulating film contains Hf and O.4. The semiconductor device according to claim 2, further comprising: aplurality of nonvolatile memory cells in a third region different fromthe first region and the second region of the semiconductor substrate,wherein each of the plurality of nonvolatile memory cells includes: athird gate insulating film formed on the semiconductor substrate in thethird region; a third gate electrode formed on the third insulatingfilm; a fourth gate insulating film which is formed on the semiconductorsubstrate in the third region and which has a charge storage film; afourth gate electrode formed on the fourth gate insulating film; thirdimpurity regions which are formed inside the semiconductor substrate soas to sandwich the third gate electrode and the fourth gate electrode inthe third region and which configure a part of a third source region anda part of a third drain region; a fourth silicide layer which is formedon the third impurity region and which contains the first metal andsilicon; a fifth silicide layer which is formed in an upper portion ofthe third gate electrode and which contains the first metal and silicon;and a sixth silicide layer which is formed in an upper portion of thefourth gate electrode and which contains the first metal and silicon,the second metal is added into the fourth silicide layer, the fifthsilicide layer and the sixth silicide layer, and a concentration of thesecond metal inside the fifth silicide layer and the sixth silicidelayer is lower than a concentration of the second metal inside thefourth silicide layer.
 5. The semiconductor device according to claim 1,wherein the first metal comprises nickel, and the second metal comprisesplatinum.
 6. The semiconductor device according to claim 5, wherein thefirst MISFET comprises an n-channel type MISFET, and a direction whichconnects the first source region and the first drain region in the firstMISFET is <110> or <100>.
 7. The semiconductor device according to claim1, wherein a crystal grain size of the first silicide layer is smallerthan a crystal grain size of the second silicide layer.
 8. A method formanufacturing a semiconductor device to provide a first MISFET in afirst region of a semiconductor substrate, comprising: (a) forming afirst gate insulating film on the semiconductor substrate in the firstregion; (b) forming a first gate electrode containing silicon on thefirst gate insulating film; (c) forming first impurity regions insidethe semiconductor substrate so as to sandwich the first gate electrodein the first region, the first impurity regions configuring a part of afirst source region and a part of a first drain region; (d) forming afirst silicide layer on the first impurity region; (e) forming a firstinsulating film on the semiconductor substrate so as to cover the firstgate electrode and the first silicide layer; (f) polishing the firstinsulating film so as to expose the first gate electrode; and (g)forming a second silicide layer on the first gate electrode, whereineach of the first and second silicide layers contains a first metal andsilicon, and also contains an additive made of a second metal differentfrom the first metal, and a concentration of the second metal inside thesecond silicide layer is lower than a concentration of the second metalinside the first silicide layer.
 9. The method for manufacturing thesemiconductor device according to claim 8, wherein the (d) furtherincludes: (d1) forming a first film made of the first metal, to whichthe second metal is added, on the first impurity region; (d2) performinga first thermal treatment onto the semiconductor substrate having thefirst film formed therein; and (d3) after the (d2), performing a secondthermal treatment, which has a temperature higher than a temperature ofthe first thermal treatment, onto the semiconductor substrate, the (g)further includes: (g1) forming a second film made of the first metal, towhich the second metal is added, on the first gate electrode; (g2)performing a third thermal treatment onto the semiconductor substratehaving the second film formed therein; and (g3) after the (g2),performing a fourth thermal treatment, which has a temperature higherthan a temperature of the third thermal treatment, onto thesemiconductor substrate, and a temperature of the fourth thermaltreatment is lower than a temperature of the second thermal treatment.10. The method for manufacturing the semiconductor device according toclaim 8, wherein the (d) further includes: (d4) forming a third filmmade of the first metal on the first impurity region; (d5)ion-implanting the second metal into the third film; (d6) after the(d5), performing a fifth thermal treatment onto the semiconductorsubstrate; and (d7) after the (d6), performing a sixth thermaltreatment, which has a temperature higher than a temperature of thefifth thermal treatment, onto the semiconductor substrate, and the (g)further includes: (g4) forming a fourth film made of the first metal onthe first gate electrode; (g5) ion-implanting the second metal into thefourth film; (g6) after the (g5), performing a seventh thermal treatmentonto the semiconductor substrate; and (g7) after the (g6), performing aneighth thermal treatment, which has a temperature higher than atemperature of the seventh thermal treatment, onto the semiconductorsubstrate, and a temperature of the eighth thermal treatment is lowerthan a temperature of the sixth thermal treatment.
 11. The method formanufacturing the semiconductor device according to claim 8, wherein the(d) further includes: (d8) forming a fifth film made of the first metalon the first impurity region; (d9) performing a ninth thermal treatmentonto the semiconductor substrate having the fifth film formed therein soas to form a first sub-silicide layer on an interface between the fifthfilm and the semiconductor substrate; (d10) performing a tenth thermaltreatment, which has a temperature higher than a temperature of theninth thermal treatment, onto the first sub-silicide layer so as to forma second sub-silicide layer; and (d11) ion-implanting the second metalinto the second sub-silicide layer, the (g) further includes: (g8)forming a sixth film made of the first metal on the first gateelectrode; (g9) performing an eleventh thermal treatment onto thesemiconductor substrate having the sixth film formed therein so as toform a third sub-silicide layer on an interface between the sixth filmand the first gate electrode; (g10) performing a twelfth thermaltreatment, which has a temperature higher than a temperature of theeleventh thermal treatment, onto the third sub-silicide layer so as toform a fourth sub-silicide layer; and (g11) ion-implanting the secondmetal into the fourth sub-silicide layer, and a temperature of thetwelfth thermal treatment is lower than a temperature of the tenththermal treatment.
 12. The method for manufacturing the semiconductordevice according to claim 9, wherein the second thermal treatment isperformed at a temperature of 400 degrees or higher, the fourth thermaltreatment is performed at a temperature of lower than 400 degrees, and aperiod of time during which the fourth thermal treatment is performed islonger than a period of time during which the second thermal treatmentis performed.
 13. The method for manufacturing the semiconductor deviceaccording to claim 8, wherein the semiconductor device includes a secondMISFET formed in a second region different from the first region of thesemiconductor substrate, the method further includes: (h) before the(b), forming a second gate insulating film on the semiconductorsubstrate in the second region; (i) in the (b), forming a dummy gateelectrode on the second gate insulating film in the second region; (j)forming second impurity regions inside the semiconductor substrate so asto sandwich the dummy gate electrode in the second region, the secondimpurity regions configuring a part of a second source region and a partof a second drain region; (k) in the (d), forming a third silicide layeron the second impurity region in the second region; (l) in the (e),forming the first insulating film on the semiconductor substrate in thesecond region so as to cover the dummy gate electrode and the thirdsilicide layer; (m) in the (f), polishing an upper surface of the firstinsulating film in the second region so as to expose the dummy gateelectrode; (n) in between the (f) and the (g), removing the dummy gateelectrode in the second region; (o) after the (n), burying a metal filmin a region from which the dummy gate electrode has been removed in thesecond region; and (p) after the (o), polishing the metal film in thesecond region so as to expose the first insulating film, the thirdsilicide layer contains the first metal and silicon, and furthercontains an additive made of the second metal, and a concentration ofthe second metal inside the second silicide layer is lower than aconcentration of the second metal in the third silicide layer.
 14. Amethod for manufacturing a semiconductor device having a plurality ofnonvolatile memory cells formed in a first region of a semiconductorsubstrate, comprising: (a) forming a first gate insulating film on thesemiconductor substrate in the first region; (b) forming a first gateelectrode on the first gate insulating film; (c) forming a second gateinsulating film having a charge storage film on the semiconductorsubstrate in the first region; (d) forming a second gate electrode onthe second gate insulating film; (e) after the (d), forming firstimpurity regions so as to sandwich the first gate electrode and thesecond gate electrode inside the semiconductor substrate in the firstregion, the first impurity regions configuring a part of a first sourceregion and a part of a first drain region; (f) forming a first silicidelayer on the first impurity region; (g) forming a first insulating filmon the semiconductor substrate so as to cover the first gate electrode,the second gate electrode and the first silicide layer; (h) polishingthe first insulating film so as to expose the first gate electrode andthe second gate electrode; and (i) forming a second silicide layer and athird silicide layer on the first gate electrode and the second gateelectrode, respectively, wherein each of the first silicide layer, thesecond silicide layer, and the third silicide layer contains a firstmetal and silicon, a second metal different from the first metal isadded into the first silicide layer, the second silicide layer, and thethird silicide layer, and a concentration of the second metal inside thesecond silicide layer and a concentration of the second metal inside thethird silicide layer are lower than a concentration of the second metalinside the first silicide layer.
 15. The method for manufacturing thesemiconductor device according to claim 14, wherein the (f) furtherincludes: (f1) forming a first film made of the first metal, to whichthe second metal is added, on the first impurity region; (f2) performinga first thermal treatment onto the semiconductor substrate having thefirst film formed therein; and (f3) after the (f2), performing a secondthermal treatment, which has a temperature higher than a temperature ofthe first thermal treatment, onto the semiconductor substrate, the (i)further includes: (i1) forming a second film made of the first metal, towhich the second metal is added, on the first gate electrode and thesecond gate electrode; (i2) performing a third thermal treatment ontothe semiconductor substrate having the second film formed therein; and(i3) after the (i2), performing a fourth thermal treatment, which has atemperature higher than a temperature of the third thermal treatment,onto the semiconductor substrate, and a temperature of the fourththermal treatment is lower than a temperature of the second thermaltreatment.
 16. The method for manufacturing the semiconductor deviceaccording to claim 14, wherein the (f) further includes: (f4) forming athird film made of the first metal on the first impurity region; (f5)ion-implanting the second metal into the third film; (f6) after the(f5), performing a fifth thermal treatment onto the semiconductorsubstrate; and (f7) after the (f6), performing a sixth thermaltreatment, which has a temperature higher a temperature of the fifththermal treatment, onto the semiconductor substrate, the (i) furtherincludes: (i4) forming a fourth film made of the first metal on thefirst gate electrode and the second gate electrode; (i5) ion-implantingthe second metal into the fourth film; (i6) after the (i5), performing aseventh thermal treatment onto the semiconductor substrate; and (i7)after the (i6), performing an eighth thermal treatment, which has atemperature higher than a temperature of the seventh thermal treatment,onto the semiconductor substrate, and a temperature of the eighththermal treatment is lower than a temperature of the sixth thermaltreatment.
 17. The method for manufacturing the semiconductor deviceaccording to claim 14, wherein the (f) further includes: (f8) forming afifth film made of the first metal on the first impurity region; (f9)performing a ninth thermal treatment onto the semiconductor substratehaving the fifth film formed therein so as to form a first sub-silicidelayer on an interface between the fifth film and the semiconductorsubstrate; (f10) performing a tenth thermal treatment, which has atemperature higher than a temperature of the ninth thermal treatment,onto the first sub-silicide layer so as to form a second sub-silicidelayer; and (f11) ion-implanting the second metal into the secondsub-silicide layer, and the (i) further includes: (i8) forming a sixthfilm made of the first metal on the first gate electrode; (i9)performing an eleventh thermal treatment onto the semiconductorsubstrate having the sixth film formed therein so as to form a thirdsub-silicide layer on an interface between the sixth film and the firstgate electrode; (i10) performing a twelfth thermal treatment, which hasa temperature higher than a temperature of the eleventh thermaltreatment, onto the third sub-silicide layer so as to form a fourthsub-silicide layer; and (i11) ion-implanting the second metal into thefourth sub-silicide layer, and a temperature of the twelfth thermaltreatment is lower than a temperature of the tenth thermal treatment.18. The method for manufacturing the semiconductor device according toclaim 15, wherein the second thermal treatment is performed at atemperature of 400 degrees or higher and 600 degrees or lower, thefourth thermal treatment is performed at a temperature lower than 400degrees, and a period of time during which the fourth thermal treatmentis performed is longer than a period of time during which the secondthermal treatment is performed.
 19. The method for manufacturing thesemiconductor device according to claim 14, wherein the semiconductordevice includes a second MISFET formed in a second region different fromthe first region of the semiconductor substrate, the method furtherincludes: (j) before the (b), forming a second gate insulating film onthe semiconductor substrate in the second region; (k) in the (b),forming a dummy gate electrode on the second gate insulating film in thesecond region; (l) forming second impurity regions inside thesemiconductor substrate in the second region so as to sandwich the dummygate electrode, the second impurity regions configuring a part of asecond source region and a part of a second drain region; (m) in the(f), forming a third silicide layer on the second impurity region in thesecond region; (n) in the (g), forming the first insulating film on thesemiconductor substrate in the second region so as to cover the dummygate electrode and the third silicide layer; (o) in the (h), polishingan upper surface of the first insulating film in the second region so asto expose the dummy gate electrode; (p) in between the (h) and the (i),removing the dummy gate electrode in the second region; (q) after the(p), burying a metal film in a region from which the dummy gateelectrode has been removed in the second region; and (r) after the (q),polishing the metal film in the second region so as to expose the firstinsulating film, the third silicide layer contains the first metal andsilicon, and further contains an additive made of the second metal, anda concentration of the second metal inside the second silicide layer islower than a concentration of the second metal inside the third silicidelayer.
 20. The method for manufacturing the semiconductor deviceaccording to claim 8, wherein the first metal comprises nickel, and thesecond metal comprises platinum.